library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity E_exam1 is
port(u: in std_logic_vector(2 downto 0) ;
     v: in std_logic_vector(2 downto 0) ;
     w: in std_logic_vector(2 downto 0) ;
     x: in std_logic_vector(2 downto 0) ;
     y: in std_logic_vector(2 downto 0) ;
     s: in std_logic_vector(2 downto 0) ;
     Displaya : OUT STD_logic_vector(0 TO 6);
     Displayb : OUT STD_logic_vector(0 TO 6);
     Displayc : OUT STD_logic_vector(0 TO 6);
     Displayd : OUT STD_logic_vector(0 TO 6);
     Displaye : OUT STD_logic_vector(0 TO 6)
);
end E_exam1;

ARCHITECTURE Behavior OF E_exam1 IS
signal a: std_logic_vector(2 downto 0); 
signal b: std_logic_vector(2 downto 0);
signal c: std_logic_vector(2 downto 0);
signal d: std_logic_vector(2 downto 0);
signal e: std_logic_vector(2 downto 0);

COMPONENT E_example1  IS
port(u: in std_logic_vector(2 downto 0) ;
     v: in std_logic_vector(2 downto 0) ;
     w: in std_logic_vector(2 downto 0) ;
     x: in std_logic_vector(2 downto 0) ;
     y: in std_logic_vector(2 downto 0) ;
     s: in std_logic_vector(2 downto 0) ;
     Display : OUT STD_logic_vector(0 TO 6)
);
end component;

begin
process(s)
begin

case s is
when "000" =>a<="000";b<="001";c<="010";d<="010";e<="100";
when "001" =>a<="001";b<="010";c<="010";d<="100";e<="000";
when "010" =>a<="010";b<="010";c<="100";d<="000";e<="001";
when "011" =>a<="010";b<="100";c<="000";d<="001";e<="010";
when "100" =>a<="100";b<="000";c<="001";d<="010";e<="010";
when others =>a<="000";b<="001";c<="010";d<="010";e<="100";
end case;
end process;

u10: E_example1 port map(u,v,w,x,y,a,displaya);
u11: E_example1 port map(u,v,w,x,y,b,displayb);
u12: E_example1 port map(u,v,w,x,y,c,displayc);
u13: E_example1 port map(u,v,w,x,y,d,displayd);
u14: E_example1 port map(u,v,w,x,y,e,displaye);

end Behavior;