library ieee;
use ieee.std_logic_1164.all;

entity E_mux51 is
port (u : in std_logic ;
      v : in std_logic ;
      w : in std_logic ;
      x : in std_logic ;
      y : in std_logic ;
      s0 : in std_logic ;
      s1 : in std_logic ;
      s2 : in std_logic ;
      m : buffer std_logic 
      );
end E_mux51;

ARCHITECTURE Behavior OF E_mux51 IS
signal out10 : std_logic;
signal out11 : std_logic;
signal out20 : std_logic;
        
COMPONENT E_mux2 IS
port (x : in std_logic ;
      y : in std_logic ;
      s : in std_logic ;
      m : buffer std_logic 
      );
END COMPONENT;

BEGIN
u1:E_mux2 PORT MAP(u,v,s0,out10);
u2:E_mux2 PORT MAP(w,x,s0,out11);
u3:E_mux2 PORT MAP(out10,out11,s1,out20);
u4:E_mux2 PORT MAP(out20,y,s2,m);


END Behavior;