?? cstartup.lst
字號:
###############################################################################
# #
# IAR Systems ARM Assembler V4.30A/W32 13/Mar/2006 09:58:59 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Source file = D:\SAM7-IAR\AT91SAM7X256-IAR\SAM7X256-AIC-IAR\AT91SAM7X256-AIC-IAR\srcIAR\Cstartup.s79#
# List file = D:\SAM7-IAR\AT91SAM7X256-IAR\SAM7X256-AIC-IAR\AT91SAM7X256-AIC-IAR\FLASH_DEBUG\List\Cstartup.lst#
# Object file = D:\SAM7-IAR\AT91SAM7X256-IAR\SAM7X256-AIC-IAR\AT91SAM7X256-AIC-IAR\FLASH_DEBUG\Obj\Cstartup.r79#
# Command line = D:\SAM7-IAR\AT91SAM7X256-IAR\SAM7X256-AIC-IAR\AT91SAM7X256-AIC-IAR\srcIAR\Cstartup.s79 #
# -OD:\SAM7-IAR\AT91SAM7X256-IAR\SAM7X256-AIC-IAR\AT91SAM7X256-AIC-IAR\FLASH_DEBUG\Obj\ #
# -s+ -M<> -w+ -r #
# -LD:\SAM7-IAR\AT91SAM7X256-IAR\SAM7X256-AIC-IAR\AT91SAM7X256-AIC-IAR\FLASH_DEBUG\List\ #
# -t8 --cpu ARM7TDMI --fpu None #
# -IC:\Program Files\IAR Systems\Embedded Workbench 4.0 Kickstart\arm\INC\ #
# -ID:\SAM7-IAR\AT91SAM7X256-IAR\SAM7X256-AIC-IAR\AT91SAM7X256-AIC-IAR\include\ #
# -ID:\SAM7-IAR\AT91SAM7X256-IAR\SAM7X256-AIC-IAR\AT91SAM7X256-AIC-IAR\srcIAR\ #
# -ID:\SAM7-IAR\AT91SAM7X256-IAR\SAM7X256-AIC-IAR\AT91SAM7X256-AIC-IAR\src\ #
# #
###############################################################################
1 00000000 ;- --------------------------------------------
--------------------------------
2 00000000 ;- ATMEL Microcontroller Software
Support - ROUSSET -
3 00000000 ;- --------------------------------------------
--------------------------------
4 00000000 ;- DISCLAIMER: THIS SOFTWARE IS PROVIDED BY
ATMEL "AS IS" AND ANY EXPRESS OR
5 00000000 ;- IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF
6 00000000 ;- MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NON-INFRINGEMENT ARE
7 00000000 ;- DISCLAIMED. IN NO EVENT SHALL ATMEL BE
LIABLE FOR ANY DIRECT, INDIRECT,
8 00000000 ;- INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT
9 00000000 ;- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES; LOSS OF USE, DATA,
10 00000000 ;- OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF
11 00000000 ;- LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING
12 00000000 ;- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE,
13 00000000 ;- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGE.
14 00000000 ;- --------------------------------------------
--------------------------------
15 00000000 ;- File source : Cstartup.s79
16 00000000 ;- Object : Generic CStartup
17 00000000 ;- 1.0 01/Sep/05 FBr : Creation
18 00000000 ;- 1.1 09/Sep/05 JPP : Change Interrupt
management
19 00000000 ;-----------------------------------------------
-------------------------------
20 00000000
21 00000000 ;-----------------------------------------------
-------------------------------
22 00000000 ; Include your AT91 Library files
23 00000000 ;-----------------------------------------------
-------------------------------
24 00000000 #include "AT91SAM7X256_inc.h"
25 00000000 ;-----------------------------------------------
-------------------------------
26 00000000
27 00000000 ;-----------------------------------------------
-------------------------------
28 00000000 ; ?RESET
29 00000000 ; Reset Vector.
30 00000000 ; Normally, segment INTVEC is linked at address
0.
31 00000000 ; For debugging purposes, INTVEC may be placed
at other addresses.
32 00000000 ; A debugger that honors the entry point will
start the
33 00000000 ; program in a normal way even if INTVEC is not
at address 0.
34 00000000 ;-----------------------------------------------
-------------------------------
35 00000000
36 00000000 PROGRAM ?RESET ;- Begins a
program module
37 00000000 RSEG INTRAMEND_REMAP ;- Begins a
relocatable segment
38 00000000 RSEG ICODE:CODE (2) ;- Begins a
relocatable segment : corresponding address is
32-bit aligned
39 00000000 CODE32 ;- Always
ARM mode after reset
40 00000000 ORG 0 ;- Sets the
location
counter:
corresponds
to the
RESET
vector
address
41 00000000
42 00000000 ;-----------------------------------------------
-------------------------------
43 00000000 ;- Exception vectors
44 00000000 ;-----------------------------------------------
-------------------------------
45 00000000 ;- These vectors can be read at address 0 or at
RAM address
46 00000000 ;- They ABSOLUTELY requires to be in relative
addresssing mode in order to
47 00000000 ;- guarantee a valid jump. For the moment, all
are just looping.
48 00000000 ;- If an exception occurs before remap, this
would result in an infinite loop.
49 00000000 ;- To ensure if a exeption occurs before start
application to infinite loop.
50 00000000 ;-----------------------------------------------
-------------------------------
51 00000000
52 00000000 reset
53 00000000 210000EA B InitReset
; 0x00 Reset handler
54 00000004 undefvec:
55 00000004 FEFFFFEA B undefvec
; 0x04 Undefined Instruction
56 00000008 swivec:
57 00000008 FEFFFFEA B swivec
; 0x08 Software Interrupt
58 0000000C pabtvec:
59 0000000C FEFFFFEA B pabtvec
; 0x0C Prefetch Abort
60 00000010 dabtvec:
61 00000010 FEFFFFEA B dabtvec
; 0x10 Data Abort
62 00000014 rsvdvec:
63 00000014 FEFFFFEA B rsvdvec
; 0x14 reserved
64 00000018 irqvec:
65 00000018 090000EA B IRQ_Handler_Entry
; 0x18 IRQ
66 0000001C
67 0000001C fiqvec:
; 0x1c FIQ
68 0000001C ;-----------------------------------------------
-------------------------------
69 0000001C ;- Function : FIQ_Handler_Entry
70 0000001C ;- Treatments : FIQ Controller
Interrupt Handler.
71 0000001C ;- Called Functions : AIC_FVR[interrupt]
72 0000001C ;-----------------------------------------------
-------------------------------
73 0000001C
74 0000001C FIQ_Handler_Entry:
75 0000001C
76 0000001C ;- Switch in SVC/User Mode to allow User Stack
access for C code
77 0000001C ; because the FIQ is not yet acknowledged
78 0000001C
79 0000001C ;- Save and r0 in FIQ_Register
80 0000001C 0090A0E1 mov r9,r0
81 00000020 040198E5 ldr r0 , [r8, #AIC_FVR]
82 00000024 D3F021E3 msr CPSR_c,#I_BIT | F_BIT |
ARM_MODE_SVC
83 00000028 ;- Save scratch/used registers and LR in User
Stack
84 00000028 0E502DE9 stmfd sp!, { r1-r3, r12,
lr}
85 0000002C
86 0000002C ;- Branch to the routine pointed by the
AIC_FVR
87 0000002C 0FE0A0E1 mov r14, pc
88 00000030 10FF2FE1 bx r0
89 00000034
90 00000034 ;- Restore scratch/used registers and LR from
User Stack
91 00000034 0E50BDE8 ldmia sp!, { r1-r3, r12,
lr}
92 00000038
93 00000038 ;- Leave Interrupts disabled and switch back in
FIQ mode
94 00000038 D1F021E3 msr CPSR_c, #I_BIT | F_BIT |
ARM_MODE_FIQ
95 0000003C
96 0000003C ;- Restore the R0 ARM_MODE_SVC register
97 0000003C 0900A0E1 mov r0,r9
98 00000040
99 00000040 ;- Restore the Program Counter using the LR_fiq
directly in the PC
100 00000040 04F05EE2 subs pc,lr,#4
101 00000044
102 00000044 ;-----------------------------------------------
-------------------------------
103 00000044 ;- Manage exception: The exception must be
ensure in ARM mode
104 00000044 ;-----------------------------------------------
-------------------------------
105 00000044 ;-----------------------------------------------
-------------------------------
106 00000044 ;- Function : IRQ_Handler_Entry
107 00000044 ;- Treatments : IRQ Controller
Interrupt Handler.
108 00000044 ;- Called Functions : AIC_IVR[interrupt]
109 00000044 ;-----------------------------------------------
-------------------------------
110 00000044 IRQ_Handler_Entry:
111 00000044
112 00000044 ;-------------------------
113 00000044 ;- Manage Exception Entry
114 00000044 ;-------------------------
115 00000044 ;- Adjust and save LR_irq in IRQ stack
116 00000044 04E04EE2 sub lr, lr, #4
117 00000048 00402DE9 stmfd sp!, {lr}
118 0000004C
119 0000004C ;- Save r0 and SPSR (need to be saved for nested
interrupt)
120 0000004C 00E04FE1 mrs r14, SPSR
121 00000050 01402DE9 stmfd sp!, {r0,r14}
122 00000054
123 00000054 ;- Write in the IVR to support Protect
Mode
124 00000054 ;- No effect in Normal Mode
125 00000054 ;- De-assert the NIRQ and clear the source in
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