?? c8051f340.h
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sfr SPI0CN = 0xF8; // SPI0 Control
sfr PCA0L = 0xF9; // PCA0 Counter Low
sfr PCA0H = 0xFA; // PCA0 Counter High
sfr PCA0CPL0 = 0xFB; // PCA0 Capture 0 Low
sfr PCA0CPH0 = 0xFC; // PCA0 Capture 0 High
sfr PCA0CPL4 = 0xFD; // PCA0 Capture 4 Low
sfr PCA0CPH4 = 0xFE; // PCA0 Capture 4 High
sfr VDM0CN = 0xFF; // VDD Monitor Control
//-----------------------------------------------------------------------------
// Bit Definitions
//-----------------------------------------------------------------------------
// TCON 0x88
sbit TF1 = 0x8F; // Timer1 overflow flag
sbit TR1 = 0x8E; // Timer1 on/off control
sbit TF0 = 0x8D; // Timer0 overflow flag
sbit TR0 = 0x8C; // Timer0 on/off control
sbit IE1 = 0x8B; // Ext interrupt 1 edge flag
sbit IT1 = 0x8A; // Ext interrupt 1 type
sbit IE0 = 0x89; // Ext interrupt 0 edge flag
sbit IT0 = 0x88; // Ext interrupt 0 type
// SCON0 0x98
sbit S0MODE = 0x9F; // Serial mode control bit 0
// Bit6 UNUSED
sbit MCE0 = 0x9D; // Multiprocessor communication enable
sbit REN0 = 0x9C; // Receive enable
sbit TB80 = 0x9B; // Transmit bit 8
sbit RB80 = 0x9A; // Receive bit 8
sbit TI0 = 0x99; // Transmit interrupt flag
sbit RI0 = 0x98; // Receive interrupt flag
// IE 0xA8
sbit EA = 0xAF; // Global interrupt enable
sbit ESPI0 = 0xAE; // SPI0 interrupt enable
sbit ET2 = 0xAD; // Timer2 interrupt enable
sbit ES0 = 0xAC; // UART0 interrupt enable
sbit ET1 = 0xAB; // Timer1 interrupt enable
sbit EX1 = 0xAA; // External interrupt 1 enable
sbit ET0 = 0xA9; // Timer0 interrupt enable
sbit EX0 = 0xA8; // External interrupt 0 enable
// IP 0xB8
// Bit7 UNUSED
sbit PSPI0 = 0xBE; // SPI0 interrupt priority
sbit PT2 = 0xBD; // Timer2 priority
sbit PS0 = 0xBC; // UART0 priority
sbit PT1 = 0xBB; // Timer1 priority
sbit PX1 = 0xBA; // External interrupt 1 priority
sbit PT0 = 0xB9; // Timer0 priority
sbit PX0 = 0xB8; // External interrupt 0 priority
// SMB0CN 0xC0
sbit MASTER = 0xC7; // Master/slave indicator
sbit TXMODE = 0xC6; // Transmit mode indicator
sbit STA = 0xC5; // Start flag
sbit STO = 0xC4; // Stop flag
sbit ACKRQ = 0xC3; // Acknowledge request
sbit ARBLOST = 0xC2; // Arbitration lost indicator
sbit ACK = 0xC1; // Acknowledge flag
sbit SI = 0xC0; // SMBus interrupt flag
// TMR2CN 0xC8
sbit TF2H = 0xCF; // Timer2 high byte overflow flag
sbit TF2L = 0xCE; // Timer2 low byte overflow flag
sbit TF2LEN = 0xCD; // Timer2 low byte interrupt enable
sbit T2CE = 0xCC; // Timer2 capture enable
sbit T2SPLIT = 0xCB; // Timer2 split mode enable
sbit TR2 = 0xCA; // Timer2 on/off control
sbit T2CSS = 0xC9; // Timer 2 Capture Source select
sbit T2XCLK = 0xC8; // Timer2 external clock select
// PSW 0xD0
sbit CY = 0xD7; // Carry flag
sbit AC = 0xD6; // Auxiliary carry flag
sbit F0 = 0xD5; // User flag 0
sbit RS1 = 0xD4; // Register bank select 1
sbit RS0 = 0xD3; // Register bank select 0
sbit OV = 0xD2; // Overflow flag
sbit F1 = 0xD1; // User flag 1
sbit P = 0xD0; // Accumulator parity flag
// PCA0CN 0xD8
sbit CF = 0xDF; // PCA0 counter overflow flag
sbit CR = 0xDE; // PCA0 counter run control
// Bit5 UNUSED
sbit CCF4 = 0xDC; // PCA0 module4 capture/compare flag
sbit CCF3 = 0xDB; // PCA0 module3 capture/compare flag
sbit CCF2 = 0xDA; // PCA0 module2 capture/compare flag
sbit CCF1 = 0xD9; // PCA0 module1 capture/compare flag
sbit CCF0 = 0xD8; // PCA0 module0 capture/compare flag
// ADC0CN 0xE8
sbit AD0EN = 0xEF; // ADC0 enable
sbit AD0TM = 0xEE; // ADC0 track mode
sbit AD0INT = 0xED; // ADC0 conversion complete interrupt flag
sbit AD0BUSY = 0xEC; // ADC0 busy flag
sbit AD0WINT = 0xEB; // ADC0 window compare interrupt flag
sbit AD0CM2 = 0xEA; // ADC0 conversion mode select 2
sbit AD0CM1 = 0xE9; // ADC0 conversion mode select 1
sbit AD0CM0 = 0xE8; // ADC0 conversion mode select 0
// SPI0CN 0xF8
sbit SPIF = 0xFF; // SPI0 interrupt flag
sbit WCOL = 0xFE; // SPI0 write collision flag
sbit MODF = 0xFD; // SPI0 mode fault flag
sbit RXOVRN = 0xFC; // SPI0 rx overrun flag
sbit NSSMD1 = 0xFB; // SPI0 slave select mode 1
sbit NSSMD0 = 0xFA; // SPI0 slave select mode 0
sbit TXBMT = 0xF9; // SPI0 transmit buffer empty
sbit SPIEN = 0xF8; // SPI0 SPI enable
//-----------------------------------------------------------------------------
// Interrupt Priorities
//-----------------------------------------------------------------------------
#define INTERRUPT_INT0 0 // External Interrupt 0
#define INTERRUPT_TIMER0 1 // Timer0 Overflow
#define INTERRUPT_INT1 2 // External Interrupt 1
#define INTERRUPT_TIMER1 3 // Timer1 Overflow
#define INTERRUPT_UART0 4 // Serial Port 0
#define INTERRUPT_TIMER2 5 // Timer2 Overflow
#define INTERRUPT_SPI0 6 // Serial Peripheral Interface 0
#define INTERRUPT_SMBUS0 7 // SMBus0 Interface
#define INTERRUPT_USB0 8 // USB Interface
#define INTERRUPT_ADC0_WINDOW 9 // ADC0 Window Comparison
#define INTERRUPT_ADC0_EOC 10 // ADC0 End Of Conversion
#define INTERRUPT_PCA0 11 // PCA0 Peripheral
#define INTERRUPT_COMPARATOR0 12 // Comparator0
#define INTERRUPT_COMPARATOR1 13 // Comparator1
#define INTERRUPT_TIMER3 14 // Timer3 Overflow
#define INTERRUPT_VBUS_LEVEL 15 // VBUS level-triggered interrupt
#define INTERRUPT_UART1 16 // Serial Port 1
//-----------------------------------------------------------------------------
// Header File PreProcessor Directive
//-----------------------------------------------------------------------------
#endif // #define C8051F340_H
//-----------------------------------------------------------------------------
// End Of File
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