/****************************************Copyright (c)****************************************************                               Guangzou ZLG-MCU Development Co.,LTD.**                                      graduate school**                                 http://www.zlgmcu.com****--------------File Info-------------------------------------------------------------------------------** File name:			mouse_register_file.v** Last modified Date:	2006-04-14** Last Version:		1.0** Descriptions:		mouse logic**------------------------------------------------------------------------------------------------------** Created by:			RuiWenBin** Created date:		2006-04-14** Version:				1.0** Descriptions:		****------------------------------------------------------------------------------------------------------** Modified by:		** Modified date:		** Version:				** Descriptions:		****------------------------------------------------------------------------------------------------------********************************************************************************************************/module mouse_register_file(		//Avalon Signals	clock,	reset_n, 	chip_select,	address,	read,	read_data,	interrupt,        //ps2_mouse_interface signals	left_button,	right_button,	middle_button,	x_increment,	y_increment,	data_ready,	reset);		input 			clock;			    //System Clock		input 			reset_n;			//System Reset		input 			chip_select;		//Avalon Chip select signal		input 		 	address;	     	//Avalon Address bus 		input 			read;			    //Avalon read signal		output [31:0] 	read_data;	  		//Avalon read data bus		output   		interrupt;			//System interrupt		input			left_button;		input			right_button;		input			middle_button;		input[8:0]		x_increment;		input[8:0]		y_increment;		input			data_ready;		output			reset;		//Signal Declarations	reg [31:0] 	read_data_r;			//Read_data busreg			data_ready_r;wire		read_act;//determine if a vaild transaction was initiated 	assign read_act  = chip_select & read; assign read_data = read_data_r;   //Read dataassign reset = ~reset_n;assign interrupt = data_ready_r;parameter		rd_data		= 1'b0;always @(posedge clock)begin	if(read_act)		data_ready_r <= 1'b0;	else if(data_ready)		data_ready_r <= 1'b1;end //read               always @(read_act 		or address 		or data_ready_r 		or left_button		or right_button		or middle_button		or x_increment		or y_increment)begin           	if (read_act)	begin       		case (address)		   rd_data:			begin				read_data_r <= {10'b0,								data_ready_r,     //1 bit								left_button,      //1 bit								right_button,     //1 bit								middle_button,    //1 bit								y_increment,      //9 bits								x_increment};     //9 bits							end			default:			begin				read_data_r <= 32'h0;			end		endcase	end	else		read_data_r <= 32'h0;endendmodule