?? jishu60.tan.qmsg
字號:
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" { } { } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學期/verilog/新建文件夾 (2)/中/jishu60.v" 2 -1 0 } } { "d:/programe files/quatus 60/win/Assignment Editor.qase" "" { Assignment "d:/programe files/quatus 60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] register jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] 100.0 MHz 10.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 100.0 MHz between source register \"jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]\" and destination register \"jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] 1 REG LC2 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "" { jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] 2 REG LC2 35 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { jishi:u1|lpm_counter:q_rtl_1|dffs[0] jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { jishi:u1|lpm_counter:q_rtl_1|dffs[0] jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "6.000 ns" { jishi:u1|lpm_counter:q_rtl_1|dffs[0] jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學期/verilog/新建文件夾 (2)/中/jishu60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] 2 REG LC2 35 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學期/verilog/新建文件夾 (2)/中/jishu60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] 2 REG LC2 35 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { jishi:u1|lpm_counter:q_rtl_1|dffs[0] jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "6.000 ns" { jishi:u1|lpm_counter:q_rtl_1|dffs[0] jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] ena clk 7.000 ns register " "Info: tsu for register \"jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]\" (data pin = \"ena\", clock pin = \"clk\") is 7.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ena 1 PIN PIN_52 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_52; Fanout = 9; PIN Node = 'ena'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "" { ena } "NODE_NAME" } } { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學期/verilog/新建文件夾 (2)/中/jishu60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] 2 REG LC2 35 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ena jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { ena jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "6.500 ns" { ena ena~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學期/verilog/新建文件夾 (2)/中/jishu60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] 2 REG LC2 35 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { ena jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "6.500 ns" { ena ena~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[14\] block1:u2\|lpm_counter:q_rtl_0\|dffs\[1\] 13.000 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[14\]\" through register \"block1:u2\|lpm_counter:q_rtl_0\|dffs\[1\]\" is 13.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學期/verilog/新建文件夾 (2)/中/jishu60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns block1:u2\|lpm_counter:q_rtl_0\|dffs\[1\] 2 REG LC9 19 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC9; Fanout = 19; REG Node = 'block1:u2\|lpm_counter:q_rtl_0\|dffs\[1\]'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk block1:u2|lpm_counter:q_rtl_0|dffs[1] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk block1:u2|lpm_counter:q_rtl_0|dffs[1] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out block1:u2|lpm_counter:q_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.500 ns + Longest register pin " "Info: + Longest register to pin delay is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns block1:u2\|lpm_counter:q_rtl_0\|dffs\[1\] 1 REG LC9 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 19; REG Node = 'block1:u2\|lpm_counter:q_rtl_0\|dffs\[1\]'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "" { block1:u2|lpm_counter:q_rtl_0|dffs[1] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns Dec7s:u4\|WideOr0~87 2 COMB LC16 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC16; Fanout = 1; COMB Node = 'Dec7s:u4\|WideOr0~87'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { block1:u2|lpm_counter:q_rtl_0|dffs[1] Dec7s:u4|WideOr0~87 } "NODE_NAME" } } { "Dec7s.v" "" { Text "E:/作業(yè)/大二第二學期/verilog/新建文件夾 (2)/中/Dec7s.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 9.500 ns q\[14\] 3 PIN PIN_4 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'q\[14\]'" { } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Dec7s:u4|WideOr0~87 q[14] } "NODE_NAME" } } { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學期/verilog/新建文件夾 (2)/中/jishu60.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "9.500 ns" { block1:u2|lpm_counter:q_rtl_0|dffs[1] Dec7s:u4|WideOr0~87 q[14] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "9.500 ns" { block1:u2|lpm_counter:q_rtl_0|dffs[1] Dec7s:u4|WideOr0~87 q[14] } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk block1:u2|lpm_counter:q_rtl_0|dffs[1] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out block1:u2|lpm_counter:q_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "9.500 ns" { block1:u2|lpm_counter:q_rtl_0|dffs[1] Dec7s:u4|WideOr0~87 q[14] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "9.500 ns" { block1:u2|lpm_counter:q_rtl_0|dffs[1] Dec7s:u4|WideOr0~87 q[14] } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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