{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 06 13:18:34 2009 " "Info: Processing started: Wed May 06 13:18:34 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jishu60 -c jishu60 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jishu60 -c jishu60" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jishu60.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file jishu60.v" { { "Info" "ISGN_ENTITY_NAME" "1 jishu60 " "Info: Found entity 1: jishu60" {  } { { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/jishu60.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jishu60 " "Info: Elaborating entity \"jishu60\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "jishi.v 1 1 " "Warning: Using design file jishi.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 jishi " "Info: Found entity 1: jishi" {  } { { "jishi.v" "" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/jishi.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jishi jishi:u1 " "Info: Elaborating entity \"jishi\" for hierarchy \"jishi:u1\"" {  } { { "jishu60.v" "u1" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/jishu60.v" 8 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishi.v(10) " "Warning (10230): Verilog HDL assignment warning at jishi.v(10): truncated value with size 32 to match size of target (4)" {  } { { "jishi.v" "" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/jishi.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "block1.v 1 1 " "Warning: Using design file block1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 block1 " "Info: Found entity 1: block1" {  } { { "block1.v" "" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/block1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "block1 block1:u2 " "Info: Elaborating entity \"block1\" for hierarchy \"block1:u2\"" {  } { { "jishu60.v" "u2" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/jishu60.v" 9 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 block1.v(10) " "Warning (10230): Verilog HDL assignment warning at block1.v(10): truncated value with size 32 to match size of target (4)" {  } { { "block1.v" "" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/block1.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Dec7s.v 1 1 " "Warning: Using design file Dec7s.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Dec7s " "Info: Found entity 1: Dec7s" {  } { { "Dec7s.v" "" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/Dec7s.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Dec7s Dec7s:u3 " "Info: Elaborating entity \"Dec7s\" for hierarchy \"Dec7s:u3\"" {  } { { "jishu60.v" "u3" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/jishu60.v" 10 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "block1:u2\|q\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"block1:u2\|q\[0\]~4\"" {  } { { "block1.v" "q\[0\]~4" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/block1.v" 9 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "jishi:u1\|q\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"jishi:u1\|q\[0\]~4\"" {  } { { "jishi.v" "q\[0\]~4" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/jishi.v" 9 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "block1:u2\|lpm_counter:q_rtl_0 " "Info: Elaborated megafunction instantiation \"block1:u2\|lpm_counter:q_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "block1:u2\|lpm_counter:q_rtl_0\|dffs\[3\] data_in GND " "Warning: Reduced register \"block1:u2\|lpm_counter:q_rtl_0\|dffs\[3\]\" with stuck data_in port to stuck value GND" {  } { { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "q\[7\] GND " "Warning: Pin \"q\[7\]\" stuck at GND" {  } { { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/jishu60.v" 3 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "q\[15\] GND " "Warning: Pin \"q\[15\]\" stuck at GND" {  } { { "jishu60.v" "" { Text "E:/作業(yè)/大二第二學(xué)期/verilog/新建文件夾 (2)/中/jishu60.v" 3 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "44 " "Info: Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "24 " "Info: Implemented 24 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 06 13:18:35 2009 " "Info: Processing ended: Wed May 06 13:18:35 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}