{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Analysis & Synthesis" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 15 10:16:12 2008 " "Info: Processing started: Fri Aug 15 10:16:12 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FPGA_pro -c FPGA_pro " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FPGA_pro -c FPGA_pro" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FPGA_pro.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file FPGA_pro.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FPGA_pro " "Info: Found entity 1: FPGA_pro" {  } { { "FPGA_pro.bdf" "" { Schematic "E:/FPGA/FPGA加密/FPGA_pro/FPGA_pro.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gollman.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file gollman.v" { { "Info" "ISGN_ENTITY_NAME" "1 gollman " "Info: Found entity 1: gollman" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/FPGA_pro/gollman.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gollstt.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file gollstt.v" { { "Info" "ISGN_ENTITY_NAME" "1 gollstt " "Info: Found entity 1: gollstt" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/FPGA_pro/gollstt.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FPGA_pro " "Info: Elaborating entity \"FPGA_pro\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0}
{ "Warning" "WGDFX_NO_SUPERSET_FOUND" "" "Warning: No superset bus at connection" {  } { { "FPGA_pro.bdf" "" { Schematic "E:/FPGA/FPGA加密/FPGA_pro/FPGA_pro.bdf" { { 592 704 704 632 "" "" } { 576 634 760 592 "wd7" "" } { 632 656 704 632 "" "" } { 616 704 840 632 "wd\[7..0\]" "" } } } }  } 0 0 "No superset bus at connection" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gollman gollman:inst " "Info: Elaborating entity \"gollman\" for hierarchy \"gollman:inst\"" {  } { { "FPGA_pro.bdf" "inst" { Schematic "E:/FPGA/FPGA加密/FPGA_pro/FPGA_pro.bdf" { { 240 328 424 336 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0}
{ "Critical Warning" "WVRFX_VERI_NO_DFF_INFERRED" "gollman.v(144) " "Critical Warning (10237): Verilog HDL warning at gollman.v(144): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/FPGA_pro/gollman.v" 144 0 0 } }  } 1 10237 "Verilog HDL warning at %1!s!: can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" 0 0 "Analysis & Synthesis" 0}
{ "Critical Warning" "WVRFX_VERI_NO_DFF_INFERRED" "gollman.v(170) " "Critical Warning (10237): Verilog HDL warning at gollman.v(170): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/FPGA_pro/gollman.v" 170 0 0 } }  } 1 10237 "Verilog HDL warning at %1!s!: can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gollstt gollstt:inst1 " "Info: Elaborating entity \"gollstt\" for hierarchy \"gollstt:inst1\"" {  } { { "FPGA_pro.bdf" "inst1" { Schematic "E:/FPGA/FPGA加密/FPGA_pro/FPGA_pro.bdf" { { 480 304 432 608 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_counter0.v 1 1 " "Warning: Using design file lpm_counter0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.v" "" { Text "E:/FPGA/FPGA加密/FPGA_pro/lpm_counter0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst6 " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst6\"" {  } { { "FPGA_pro.bdf" "inst6" { Schematic "E:/FPGA/FPGA加密/FPGA_pro/FPGA_pro.bdf" { { 592 512 656 688 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst6\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst6\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.v" "lpm_counter_component" { Text "E:/FPGA/FPGA加密/FPGA_pro/lpm_counter0.v" 68 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:inst6\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"lpm_counter0:inst6\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.v" "" { Text "E:/FPGA/FPGA加密/FPGA_pro/lpm_counter0.v" 68 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ihi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_ihi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ihi " "Info: Found entity 1: cntr_ihi" {  } { { "db/cntr_ihi.tdf" "" { Text "E:/FPGA/FPGA加密/FPGA_pro/db/cntr_ihi.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ihi lpm_counter0:inst6\|lpm_counter:lpm_counter_component\|cntr_ihi:auto_generated " "Info: Elaborating entity \"cntr_ihi\" for hierarchy \"lpm_counter0:inst6\|lpm_counter:lpm_counter_component\|cntr_ihi:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 272 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0}
{ "Error" "ESGN_NODE_MISSING_SOURCE" "wd7 " "Error: Node \"wd7\" is missing source" {  } { { "FPGA_pro.bdf" "wd7" { Schematic "E:/FPGA/FPGA加密/FPGA_pro/FPGA_pro.bdf" { { 576 634 760 592 "wd7" "" } } } }  } 0 0 "Node \"%1!s!\" is missing source" 0 0 "Analysis & Synthesis" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  4 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "Analysis & Synthesis" 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Aug 15 10:16:15 2008 " "Error: Processing ended: Fri Aug 15 10:16:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Analysis & Synthesis" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 1  4 s " "Error: Quartus II Full Compilation was unsuccessful. 1 error, 4 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0}