{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Analysis & Synthesis" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 15 09:45:28 2008 " "Info: Processing started: Fri Aug 15 09:45:28 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gollman -c gollman " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gollman -c gollman" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gollman.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file gollman.v" { { "Info" "ISGN_ENTITY_NAME" "1 gollman " "Info: Found entity 1: gollman" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "gollman " "Info: Elaborating entity \"gollman\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0}
{ "Critical Warning" "WVRFX_VERI_NO_DFF_INFERRED" "gollman.v(143) " "Critical Warning (10237): Verilog HDL warning at gollman.v(143): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 143 0 0 } }  } 1 10237 "Verilog HDL warning at %1!s!: can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" 0 0 "Analysis & Synthesis" 0}
{ "Critical Warning" "WVRFX_VERI_NO_DFF_INFERRED" "gollman.v(169) " "Critical Warning (10237): Verilog HDL warning at gollman.v(169): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 169 0 0 } }  } 1 10237 "Verilog HDL warning at %1!s!: can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 168 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 142 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 77 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 121 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 142 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 77 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 99 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 121 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 142 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 77 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 99 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 142 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 77 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 142 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 142 -1 0 } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 142 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "44 " "Info: Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "Analysis & Synthesis" 0} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "Analysis & Synthesis" 0} { "Info" "ICUT_CUT_TM_LCELLS" "35 " "Info: Implemented 35 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "148 " "Info: Allocated 148 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "Analysis & Synthesis" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 15 09:45:30 2008 " "Info: Processing ended: Fri Aug 15 09:45:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Analysis & Synthesis" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0}