{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Analysis & Synthesis" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 14 22:22:24 2008 " "Info: Processing started: Thu Aug 14 22:22:24 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gollstt -c gollstt " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gollstt -c gollstt" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gollstt.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file gollstt.v" { { "Info" "ISGN_ENTITY_NAME" "1 gollstt " "Info: Found entity 1: gollstt" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "donel gollstt.v(41) " "Error (10161): Verilog HDL error at gollstt.v(41): object \"donel\" is not declared" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 41 0 0 } }  } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Analysis & Synthesis" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "138 " "Info: Allocated 138 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "Analysis & Synthesis" 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Aug 14 22:22:27 2008 " "Error: Processing ended: Thu Aug 14 22:22:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Analysis & Synthesis" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 1  0 s " "Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0}