{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 14 22:23:11 2008 " "Info: Processing started: Thu Aug 14 22:23:11 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Classic Timing Analyzer" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off gollstt -c gollstt " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off gollstt -c gollstt" {  } {  } 0 0 "Command: %1!s!" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "Classic Timing Analyzer" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "Classic Timing Analyzer" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 16 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "Classic Timing Analyzer" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "Classic Timing Analyzer" 0}