LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY f_suber8 IS 
PORT(fx8,fy8 :IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
sub_in8: IN STD_LOGIC; 
diff8: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); 
s_out8: OUT STD_LOGIC); 
END ENTITY f_suber8; 
ARCHITECTURE behav OF f_suber8 IS 
COMPONENT f_suber 
PORT(fx,fy,sub_in:IN STD_LOGIC; 
diffr,sub_out:OUT STD_LOGIC); 
END COMPONENT; 
SIGNAL s_outs: STD_LOGIC_VECTOR(6 DOWNTO 0); 
BEGIN 
u1 : f_suber PORT MAP(fx=>fx8(0),fy=>fy8(0),sub_in=>sub_in8,diffr=>diff8(0),sub_out=>s_outs(0)); 
u2 : f_suber PORT MAP(fx=>fx8(1),fy=>fy8(1),sub_in=>s_outs(0),diffr=>diff8(1),sub_out=>s_outs(1)); 
u3 : f_suber PORT MAP(fx=>fx8(2),fy=>fy8(2),sub_in=>s_outs(1),diffr=>diff8(2),sub_out=>s_outs(2)); 
u4 : f_suber PORT MAP(fx=>fx8(3),fy=>fy8(3),sub_in=>s_outs(2),diffr=>diff8(3),sub_out=>s_outs(3)); 
u5 : f_suber PORT MAP(fx=>fx8(4),fy=>fy8(4),sub_in=>s_outs(3),diffr=>diff8(4),sub_out=>s_outs(4)); 
u6 : f_suber PORT MAP(fx=>fx8(5),fy=>fy8(5),sub_in=>s_outs(4),diffr=>diff8(5),sub_out=>s_outs(5)); 
u7 : f_suber PORT MAP(fx=>fx8(6),fy=>fy8(6),sub_in=>s_outs(5),diffr=>diff8(6),sub_out=>s_outs(6)); 
u8 : f_suber PORT MAP(fx=>fx8(7),fy=>fy8(7),sub_in=>s_outs(6),diffr=>diff8(7),sub_out=>s_out8); 
END behav;