LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY f_suber is 
PORT(fx,fy,sub_in:IN STD_LOGIC; 
diffr,sub_out:OUT STD_LOGIC); 
END ENTITY f_suber; 
ARCHITECTURE behav OF f_suber IS 
COMPONENT h_suber 
PORT(x,y : IN STD_LOGIC; 
diff,s_out:OUT STD_LOGIC); 
END COMPONENT; 
SIGNAL a,b,c : STD_LOGIC; 
BEGIN 
u1:h_suber PORT MAP(x=>fx,y=>fy,diff=>a,s_out=>b); 
u2:h_suber PORT MAP(x=>a,y=>sub_in,diff=>diffr,s_out=>c); 
sub_out<=b or c; 
END behav;