?? f_suber8.tan.rpt
字號:
Timing Analyzer report for f_suber8
Tue Mar 31 20:23:53 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+----------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.446 ns ; fx8[0] ; diff8[7] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+---------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+---------+----------+
; N/A ; None ; 13.446 ns ; fx8[0] ; diff8[7] ;
; N/A ; None ; 13.377 ns ; fy8[0] ; diff8[7] ;
; N/A ; None ; 13.267 ns ; sub_in8 ; diff8[7] ;
; N/A ; None ; 13.028 ns ; fx8[0] ; s_out8 ;
; N/A ; None ; 13.012 ns ; fx8[0] ; diff8[6] ;
; N/A ; None ; 12.959 ns ; fy8[0] ; s_out8 ;
; N/A ; None ; 12.959 ns ; fx8[1] ; diff8[7] ;
; N/A ; None ; 12.943 ns ; fy8[0] ; diff8[6] ;
; N/A ; None ; 12.849 ns ; sub_in8 ; s_out8 ;
; N/A ; None ; 12.833 ns ; sub_in8 ; diff8[6] ;
; N/A ; None ; 12.596 ns ; fy8[1] ; diff8[7] ;
; N/A ; None ; 12.548 ns ; fx8[2] ; diff8[7] ;
; N/A ; None ; 12.541 ns ; fx8[1] ; s_out8 ;
; N/A ; None ; 12.525 ns ; fx8[1] ; diff8[6] ;
; N/A ; None ; 12.414 ns ; fx8[0] ; diff8[5] ;
; N/A ; None ; 12.345 ns ; fy8[0] ; diff8[5] ;
; N/A ; None ; 12.235 ns ; sub_in8 ; diff8[5] ;
; N/A ; None ; 12.178 ns ; fy8[1] ; s_out8 ;
; N/A ; None ; 12.162 ns ; fy8[1] ; diff8[6] ;
; N/A ; None ; 12.130 ns ; fx8[2] ; s_out8 ;
; N/A ; None ; 12.114 ns ; fx8[2] ; diff8[6] ;
; N/A ; None ; 12.027 ns ; fx8[0] ; diff8[4] ;
; N/A ; None ; 11.958 ns ; fy8[0] ; diff8[4] ;
; N/A ; None ; 11.927 ns ; fx8[1] ; diff8[5] ;
; N/A ; None ; 11.908 ns ; fy8[2] ; diff8[7] ;
; N/A ; None ; 11.848 ns ; sub_in8 ; diff8[4] ;
; N/A ; None ; 11.564 ns ; fy8[1] ; diff8[5] ;
; N/A ; None ; 11.540 ns ; fx8[1] ; diff8[4] ;
; N/A ; None ; 11.516 ns ; fx8[2] ; diff8[5] ;
; N/A ; None ; 11.490 ns ; fy8[2] ; s_out8 ;
; N/A ; None ; 11.474 ns ; fy8[2] ; diff8[6] ;
; N/A ; None ; 11.408 ns ; fx8[0] ; diff8[3] ;
; N/A ; None ; 11.339 ns ; fy8[0] ; diff8[3] ;
; N/A ; None ; 11.229 ns ; sub_in8 ; diff8[3] ;
; N/A ; None ; 11.177 ns ; fy8[1] ; diff8[4] ;
; N/A ; None ; 11.129 ns ; fx8[2] ; diff8[4] ;
; N/A ; None ; 10.921 ns ; fx8[1] ; diff8[3] ;
; N/A ; None ; 10.876 ns ; fy8[2] ; diff8[5] ;
; N/A ; None ; 10.677 ns ; fx8[3] ; diff8[7] ;
; N/A ; None ; 10.558 ns ; fy8[1] ; diff8[3] ;
; N/A ; None ; 10.510 ns ; fx8[2] ; diff8[3] ;
; N/A ; None ; 10.489 ns ; fy8[2] ; diff8[4] ;
; N/A ; None ; 10.398 ns ; fy8[3] ; diff8[7] ;
; N/A ; None ; 10.259 ns ; fx8[3] ; s_out8 ;
; N/A ; None ; 10.243 ns ; fx8[3] ; diff8[6] ;
; N/A ; None ; 10.107 ns ; fx8[4] ; diff8[7] ;
; N/A ; None ; 9.980 ns ; fy8[3] ; s_out8 ;
; N/A ; None ; 9.964 ns ; fy8[3] ; diff8[6] ;
; N/A ; None ; 9.870 ns ; fy8[2] ; diff8[3] ;
; N/A ; None ; 9.807 ns ; fx8[6] ; diff8[7] ;
; N/A ; None ; 9.689 ns ; fx8[4] ; s_out8 ;
; N/A ; None ; 9.673 ns ; fx8[4] ; diff8[6] ;
; N/A ; None ; 9.645 ns ; fx8[3] ; diff8[5] ;
; N/A ; None ; 9.597 ns ; fx8[5] ; diff8[7] ;
; N/A ; None ; 9.594 ns ; fx8[0] ; diff8[2] ;
; N/A ; None ; 9.525 ns ; fy8[0] ; diff8[2] ;
; N/A ; None ; 9.512 ns ; fy8[4] ; diff8[7] ;
; N/A ; None ; 9.415 ns ; sub_in8 ; diff8[2] ;
; N/A ; None ; 9.389 ns ; fx8[6] ; s_out8 ;
; N/A ; None ; 9.374 ns ; fx8[6] ; diff8[6] ;
; N/A ; None ; 9.366 ns ; fy8[3] ; diff8[5] ;
; N/A ; None ; 9.258 ns ; fx8[3] ; diff8[4] ;
; N/A ; None ; 9.206 ns ; fy8[5] ; diff8[7] ;
; N/A ; None ; 9.179 ns ; fx8[5] ; s_out8 ;
; N/A ; None ; 9.163 ns ; fx8[5] ; diff8[6] ;
; N/A ; None ; 9.107 ns ; fx8[1] ; diff8[2] ;
; N/A ; None ; 9.094 ns ; fy8[4] ; s_out8 ;
; N/A ; None ; 9.078 ns ; fy8[4] ; diff8[6] ;
; N/A ; None ; 9.075 ns ; fx8[4] ; diff8[5] ;
; N/A ; None ; 9.052 ns ; fx8[0] ; diff8[1] ;
; N/A ; None ; 8.983 ns ; fy8[0] ; diff8[1] ;
; N/A ; None ; 8.979 ns ; fy8[3] ; diff8[4] ;
; N/A ; None ; 8.873 ns ; sub_in8 ; diff8[1] ;
; N/A ; None ; 8.793 ns ; fy8[7] ; diff8[7] ;
; N/A ; None ; 8.788 ns ; fy8[5] ; s_out8 ;
; N/A ; None ; 8.772 ns ; fy8[5] ; diff8[6] ;
; N/A ; None ; 8.744 ns ; fy8[1] ; diff8[2] ;
; N/A ; None ; 8.694 ns ; fx8[2] ; diff8[2] ;
; N/A ; None ; 8.690 ns ; fx8[4] ; diff8[4] ;
; N/A ; None ; 8.659 ns ; fx8[0] ; diff8[0] ;
; N/A ; None ; 8.639 ns ; fx8[3] ; diff8[3] ;
; N/A ; None ; 8.596 ns ; fy8[6] ; diff8[7] ;
; N/A ; None ; 8.592 ns ; fy8[0] ; diff8[0] ;
; N/A ; None ; 8.567 ns ; fx8[5] ; diff8[5] ;
; N/A ; None ; 8.564 ns ; fx8[1] ; diff8[1] ;
; N/A ; None ; 8.482 ns ; sub_in8 ; diff8[0] ;
; N/A ; None ; 8.480 ns ; fy8[4] ; diff8[5] ;
; N/A ; None ; 8.375 ns ; fy8[7] ; s_out8 ;
; N/A ; None ; 8.368 ns ; fy8[3] ; diff8[3] ;
; N/A ; None ; 8.242 ns ; fx8[7] ; diff8[7] ;
; N/A ; None ; 8.201 ns ; fy8[1] ; diff8[1] ;
; N/A ; None ; 8.178 ns ; fy8[6] ; s_out8 ;
; N/A ; None ; 8.171 ns ; fy8[5] ; diff8[5] ;
; N/A ; None ; 8.162 ns ; fy8[6] ; diff8[6] ;
; N/A ; None ; 8.093 ns ; fy8[4] ; diff8[4] ;
; N/A ; None ; 8.054 ns ; fy8[2] ; diff8[2] ;
; N/A ; None ; 7.822 ns ; fx8[7] ; s_out8 ;
+-------+-------------------+-----------------+---------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Mar 31 20:23:52 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off f_suber8 -c f_suber8 --timing_analysis_only
Info: Longest tpd from source pin "fx8[0]" to destination pin "diff8[7]" is 13.446 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA20; Fanout = 2; PIN Node = 'fx8[0]'
Info: 2: + IC(3.684 ns) + CELL(0.366 ns) = 5.137 ns; Loc. = LC_X1_Y1_N9; Fanout = 2; COMB Node = 'f_suber:u1|sub_out'
Info: 3: + IC(0.322 ns) + CELL(0.075 ns) = 5.534 ns; Loc. = LC_X1_Y1_N5; Fanout = 2; COMB Node = 'f_suber:u2|sub_out'
Info: 4: + IC(0.336 ns) + CELL(0.183 ns) = 6.053 ns; Loc. = LC_X1_Y1_N6; Fanout = 2; COMB Node = 'f_suber:u3|sub_out'
Info: 5: + IC(1.552 ns) + CELL(0.280 ns) = 7.885 ns; Loc. = LC_X1_Y11_N1; Fanout = 2; COMB Node = 'f_suber:u4|sub_out'
Info: 6: + IC(0.328 ns) + CELL(0.280 ns) = 8.493 ns; Loc. = LC_X1_Y11_N9; Fanout = 2; COMB Node = 'f_suber:u5|sub_out'
Info: 7: + IC(0.322 ns) + CELL(0.075 ns) = 8.890 ns; Loc. = LC_X1_Y11_N5; Fanout = 2; COMB Node = 'f_suber:u6|sub_out'
Info: 8: + IC(0.331 ns) + CELL(0.280 ns) = 9.501 ns; Loc. = LC_X1_Y11_N2; Fanout = 2; COMB Node = 'f_suber:u7|sub_out'
Info: 9: + IC(0.323 ns) + CELL(0.075 ns) = 9.899 ns; Loc. = LC_X1_Y11_N3; Fanout = 1; COMB Node = 'f_suber:u8|h_suber:u2|diff'
Info: 10: + IC(1.171 ns) + CELL(2.376 ns) = 13.446 ns; Loc. = PIN_M17; Fanout = 0; PIN Node = 'diff8[7]'
Info: Total cell delay = 5.077 ns ( 37.76 % )
Info: Total interconnect delay = 8.369 ns ( 62.24 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Mar 31 20:23:53 2009
Info: Elapsed time: 00:00:01
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -