?? hsic2.mdl
字號(hào):
Model {
Name "HSIC2"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Wed Apr 01 16:49:06 2009"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "new"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Thu Apr 02 18:28:06 2009"
ModelVersionFormat "1.%<AutoIncrement:4>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Derivative
}
Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
ZeroCross on
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
SampleTime "-1"
VectorParams1D on
ZeroCross on
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType TransportDelay
DelayTime "1"
InitialInput "0"
BufferSize "1024"
PadeOrder "0"
TransDelayFeedthrough off
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "HSIC2"
Location [2, 82, 1014, 721]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Step
Name "1"
Position [15, 330, 45, 360]
SampleTime "0"
}
Block {
BlockType Derivative
Name "Derivative"
Position [880, 140, 910, 170]
}
Block {
BlockType Product
Name "Divide"
Ports [2, 1]
Position [355, 186, 375, 399]
Inputs "*/"
ShowAdditionalParam on
InputSameDT off
OutDataTypeMode "Specify via dialog"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType "S-Function"
Name "I-regulate"
Ports [1, 1]
Position [220, 95, 280, 125]
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [615, 200, 645, 230]
}
Block {
BlockType Integrator
Name "Integrator1"
Ports [1, 1]
Position [885, 260, 915, 290]
}
Block {
BlockType "S-Function"
Name "M"
Ports [1, 1]
Position [90, 330, 150, 360]
}
Block {
BlockType Product
Name "Multiply"
Ports [2, 1]
Position [265, 172, 285, 303]
Inputs "**"
ShowAdditionalParam on
InputSameDT off
OutDataTypeMode "Specify via dialog"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Mux
Name "Mux"
Ports [4, 1]
Position [955, 125, 970, 365]
ShowName off
DisplayOption "bar"
}
Block {
BlockType "S-Function"
Name "S-Function1"
Ports [1, 1]
Position [345, 95, 405, 125]
ShowName off
}
Block {
BlockType "S-Function"
Name "S-Function2"
Ports [1, 1]
Position [520, 45, 580, 75]
Orientation "left"
NamePlacement "alternate"
}
Block {
BlockType Sum
Name "Subtract"
Ports [2, 1]
Position [520, 145, 535, 285]
ShowAdditionalParam on
InputSameDT off
OutDataTypeMode "Specify via dialog"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [735, 205, 755, 225]
ShowName off
IconShape "round"
Inputs "|-+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [190, 145, 210, 165]
ShowName off
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Step
Name "Tin"
Position [70, 140, 100, 170]
SampleTime "0"
}
Block {
BlockType TransportDelay
Name "Transport\nDelay"
Position [790, 200, 820, 230]
}
Block {
BlockType TransportDelay
Name "Transport\nDelay1"
Position [315, 45, 345, 75]
Orientation "left"
NamePlacement "alternate"
}
Block {
BlockType Step
Name "user-set"
Position [665, 260, 695, 290]
SampleTime "0"
}
Block {
BlockType Step
Name "water -flux\n"
Position [15, 255, 45, 285]
SampleTime "0"
}
Line {
SrcBlock "Integrator"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Subtract"
SrcPort 1
Points [40, 0]
Branch {
DstBlock "Integrator"
DstPort 1
}
Branch {
Points [0, 245; -380, 0]
DstBlock "Sum1"
DstPort 2
}
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Transport\nDelay"
DstPort 1
}
Line {
SrcBlock "Derivative"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Integrator1"
SrcPort 1
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "Transport\nDelay"
SrcPort 1
Points [25, 0]
Branch {
DstBlock "Mux"
DstPort 2
}
Branch {
Points [0, -60]
DstBlock "Derivative"
DstPort 1
}
Branch {
Points [0, 60]
DstBlock "Integrator1"
DstPort 1
}
}
Line {
SrcBlock "user-set"
SrcPort 1
Points [45, 0]
Branch {
DstBlock "Sum"
DstPort 2
}
Branch {
Points [0, 60]
DstBlock "Mux"
DstPort 4
}
}
Line {
SrcBlock "Tin"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Sum1"
SrcPort 1
Points [25, 0; 0, 50]
DstBlock "Multiply"
DstPort 1
}
Line {
SrcBlock "water -flux\n"
SrcPort 1
DstBlock "Multiply"
DstPort 2
}
Line {
SrcBlock "1"
SrcPort 1
DstBlock "M"
DstPort 1
}
Line {
SrcBlock "M"
SrcPort 1
DstBlock "Divide"
DstPort 2
}
Line {
SrcBlock "Multiply"
SrcPort 1
DstBlock "Divide"
DstPort 1
}
Line {
SrcBlock "Divide"
SrcPort 1
Points [70, 0; 0, -45]
DstBlock "Subtract"
DstPort 2
}
Line {
SrcBlock "Mux"
SrcPort 1
Points [20, 0; 0, -185]
DstBlock "S-Function2"
DstPort 1
}
Line {
SrcBlock "S-Function2"
SrcPort 1
DstBlock "Transport\nDelay1"
DstPort 1
}
Line {
SrcBlock "Transport\nDelay1"
SrcPort 1
Points [-160, 0; 0, 50]
DstBlock "I-regulate"
DstPort 1
}
Line {
SrcBlock "S-Function1"
SrcPort 1
Points [40, 0; 0, 70]
DstBlock "Subtract"
DstPort 1
}
Line {
SrcBlock "I-regulate"
SrcPort 1
DstBlock "S-Function1"
DstPort 1
}
Annotation {
Name "Cp-M"
Position [371, 135]
}
}
}
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