?? frequency.c
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//USB/Normal(bits 0) 0 Clock mode select: 0 = Normal
//----- 0001 0000 0000 1100
mcbsp0_write_rdy(0x1201); //REG9 Digital Interface Activation
asm(" nop "); //Address (bits 15-9) 0001001
//X (bits 8-1) 00000000 Reserved
//ACT (bits 0) 1 Activate interface 1 = Active
//----- 0001 0010 0000 0001
Delay(0); //延遲 4000*CPU 時鐘周期
asm(" nop ");
}
/*
*************************************************************************
- 函數(shù)名稱 : void mcbsp0_write_rdy(UINT16 out_data);
- 函數(shù)說明 : MCBSP0發(fā)送一個數(shù)據(jù)
- 輸入?yún)?shù) : data
- 輸出參數(shù) : 無
- 補充說明 : 內(nèi)部帶是否發(fā)送完成的判斷
**************************************************************************
*/
void mcbsp0_write_rdy(UINT16 out_data)
{
UINT16 j;
*(unsigned int*)McBSP0_SPSA=0x0001; //McBSP0_SPSA 指向 SPCR2
while ((*(unsigned int *)McBSP0_SPSD&0x0002)==0);
//mask XRDY bit,XRDY = 1 Transmitter is ready for new data in DXR[1,2].
for(j=0;j<50;j++); //delay
*(unsigned int *)McBSP0_DXR1= out_data;
}
/*
*************************************************************************
- 函數(shù)名稱 : void mcbsp0_init_SPI(void);
- 函數(shù)說明 : MCBSP0設(shè)置為SPI模式
- 輸入?yún)?shù) : 無
- 輸出參數(shù) : 無
- 補充說明 :
**************************************************************************
*/
void mcbsp0_init_SPI(void)
{
//--------------------------------------------------------
//復(fù)位 McBSP0
*(unsigned int*)McBSP0_SPSA=0x0000;//SPCR1
*(unsigned int*)McBSP0_SPSD=0x0000;//設(shè)置SPCR1.0(RRST=0)
*(unsigned int*)McBSP0_SPSA=0x0001;//SPCR2
*(unsigned int*)McBSP0_SPSD=0x0000;//設(shè)置SPCR1.0(XRST=0)
//---------------------------------------------------------
//延遲
Delay(0); //延遲 4000*CPU 時鐘周期
//等待復(fù)位穩(wěn)定
//---------------------------------------------------------
//配置 McBSP0為 SPI 模式
*(unsigned int*)McBSP0_SPSA=0x0000;//SPCR1
*(unsigned int*)McBSP0_SPSD=0x1800;
//DLB (bit 15) 0 Digital loop back mode disabled
//RJUST (bit 14-13) 00 Right-justify and zero-fill MSBs in DRR[1,2]
//CLKSTP (bit 12-11) 11
//X (bit 10-8) 000 Reserved
//DXENA (bit 7) 0 data transmit delay bit.DX enabler is off
//ABIS (bit 6) 0 A-bis mode is disabled
//RINTM (bit 5-4) 00 RINT driven by RRDY
//RSYNER (bit 3) 0 No synchronization error
//RFULL (bit 2) 0 RBR[1,2] is not in overrun condition
//RRDY (bit 1) 0 Receiver is not ready
//RRST (bit 0) 0 Serial port receiver is disabled and in reset state
//---------- 0001 1000 0000 0000
*(unsigned int*)McBSP0_SPSA=0x0001;//SPCR2
*(unsigned int*)McBSP0_SPSD=0x0000;
//X (bit 15-10) 000000 Reseved
//FREE (bit 9) 0 Free running mode is disabled
//SOFT (bit 8) 0 SOFT mode is disabled
//FRST (bit 7) 0 Frame-synchronization logic is reset.
//GRST (bit 6) 0 Sample rate generator is reset
//XINTM (bit 5-4) 00 XINT driven by XRDY
//XSYNER (bit 3) 0 No synchronization error
//XEMPTY (bit 2) 0 XSR[1,2] is empty
//XRDY (bit 1) 0 Transmitter is not ready
//XRST (bit 0) 0 serial port transmitter is disabled and in reset state
//---------- 0000 0000 0000 0000
*(unsigned int*)McBSP0_SPSA=0x000E;//PCR
*(unsigned int*)McBSP0_SPSD=0x0A0C;
//X (bit 15-14) 00 Reseved
//XIOEN (bit 13) 0 DX, FSX and CLKX are configured as serial port
//RIOEN (bit 12) 0 DR, FSR, CLKR and CLKS are configured as serial port
//FSXM (bit 11 1 Frame synchronization is determined by the sample rate
//generator
//FSRM (bit 10) 0 Frame-synchronization pulses generated by an external
//device. FSR is an input pin
//CLKXM (bit 9) 1 CLKX is an output pin and is driven by the internal sample
//rate generator.
//CLKRM (bit 8) 0 Receive clock (CLKR) is an input driven by an external
//X (bit 7) 0 Reserved
//CLKS_STAT(bit 6) 0 CLKS pin status.
//DX_STAT (bit 5) 0 DX pin status.
//DR_STAT (bit 4) 0 DR pin status.
//FSXP (bit 3) 1 Frame-synchronization pulse FSX is active low
//FSRP (bit 2) 1 Frame-synchronization pulse FSR is active low
//CLKXP (bit 1) 0 Transmit data sampled on rising edge of CLKX
//CLKRP (bit 0) 0 Receive data sampled on falling edge of CLKR
//---------- 0000 1010 0000 1100
*(unsigned int*)McBSP0_SPSA=0x0002;//RCR1
*(unsigned int*)McBSP0_SPSD=0x0040;//
//X (bit 15) 0 Reserved
//RFRLEN1 (bit 14-8) 0000000 Receive Frame Length 1,RFRLEN1 = 000 0000 1 word per frame
//RWDLEN1 (bit 7-5) 010 Receive Word Length 1,RWDLEN1 = 010 16 bits
//X (bit 4-0) 00000 Reserved
//----- 0000 0000 0100 0000
*(unsigned int*)McBSP0_SPSA=0x0003;//RCR2
*(unsigned int*)McBSP0_SPSD=0x0041;//
//RPHASE (bit 15) 0 Receive Phases，RPHASE = 0 Single-phase frame
//RFRLEN2 (bit 14-8) 0000000 Receive Frame Length 2，RFRLEN2 = 000 0000 1 word per frame
//RWDLEN2 (bit 7-5) 010 Receive Word Length 2，RWDLEN2 = 010 16 bits
//RCOMPAND(bit 4-3) 00 No companding,
//RFIG (bit 2) 0 Receive Frame Ignore
//RDATDLY (bit 1-0) 01 Receive data delay，1-bit data delay
//----- 0000 0000 0100 0001
*(unsigned int*)McBSP0_SPSA=0x0004;//XCR1
*(unsigned int*)McBSP0_SPSD=0x0040;
//X (bit 15) 0 Reserved
//XFRLEN1 (bit 14-8) 0000000 Transmit Frame Length 1,RFRLEN1 = 000 0000 1 word per frame
//XWDLEN1 (bit 7-5) 010 Transmit Word Length 1,RWDLEN1 = 010 16 bits
//X (bit 4-0) 00000 Reserved
//----- 0000 0000 0100 0000
*(unsigned int*)McBSP0_SPSA=0x0005;//XCR2
*(unsigned int*)McBSP0_SPSD=0x0041;
//XPHASE (bit 15) 0 Transmit Phases，RPHASE = 0 Single-phase frame
//XFRLEN2 (bit 14-8) 0000000 Transmit Frame Length 2，RFRLEN2 = 000 0000 1 word per frame
//XWDLEN2 (bit 7-5) 010 Transmit Word Length 2，RWDLEN2 = 010 16 bits
//XCOMPAND(bit 4-3) 00 No companding,
//XFIG (bit 2) 0 Transmit Frame Ignore
//XDATDLY (bit 1-0) 01 Transmit data delay，1-bit data delay
//----- 0000 0000 0100 0001
*(unsigned int*)McBSP0_SPSA=0x0006;//SRGR1
*(unsigned int*)McBSP0_SPSD=0x0063;
//FWID (bit 15-8) 00000000 Frame Width
//CLKGDV (bit 7-0) 0110 0100 Sample Rate Generator Clock Divider
//CLKG = CPUCLOCK/(CLKGDV+1)
// WHEN CPUCLOCK=10MHZ，CLKG=100K
//---- 0000 0000 0110 0011
*(unsigned int*)McBSP0_SPSA=0x0007;//SRGR2
*(unsigned int*)McBSP0_SPSD=0x2000;
//GSYNC (bit 15) 0 don't care
//CLKSP (bit 14) 0 don't care
//CLKSM (bit 13) 1 Sample rate generator clock derived from CPU clock
//FSGM (bit 12) 0 Sample Rate Generator Transmit Frame-Synchronization Mode
//in spi mode,must be =0
//FPER (bit 11-0) 000000000000 Frame Period，this bits ignored
//------- 0010 0000 0000 0000
*(unsigned int*)McBSP0_SPSA=0x0001;//SPCR2
*(unsigned int*)McBSP0_SPSD=(*(unsigned int*)McBSP0_SPSD)|0x0040;
//GRST = 1 Sample rate generator is pulled out of reset
//延遲
Delay(0); //延遲 4000*CPU 時鐘周期
//等待時鐘穩(wěn)定
*(unsigned int*)McBSP0_SPSA=0x0000;//SPCR1
*(unsigned int*)McBSP0_SPSD=(*(unsigned int*)McBSP0_SPSD)|0x0001;
//RRST=1?? 快捷鍵說明
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