?? lpc214x.h
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/*****************************************************************************
* LPC214X.h: Header file for Philips LPC214x Family Microprocessors
* The header file is the super set of all hardware definition of the
* peripherals for the LPC214x family microprocessor. This information
* is provided "as is" and will not be supported or maintained by Philips.
* We do not guarantee that this information will meet your design requirements.
* For complete terms and conditions, please visit
* www.semiconductors.philips.com/acrobat_download/other/usb/generic_shrinkwrap_license_driver.pdf
*
* Copyright(C) 2005, Philips Semiconductors
* All rights reserved.
* History
* 2005.10.01 ver 1.00 Prelimnary version, first Release
* 2005.10.13 ver 1.01 Removed CSPR and DC_REVISION register.
* CSPR can not be accessed at the user level,
* DC_REVISION is no long available.
* All registers use "volatile unsigned long".
******************************************************************************/
#ifndef __LPC214x_H
#define __LPC214x_H
/* Vectored Interrupt Controller (VIC) */
#define VIC_BASE_ADDR 0xFFFFF000
#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C))
#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010))
#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014))
#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018))
#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C))
#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020))
#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x030))
#define VICDefVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x034))
#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100))
#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104))
#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108))
#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C))
#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110))
#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114))
#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118))
#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C))
#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120))
#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124))
#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128))
#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C))
#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130))
#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134))
#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138))
#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C))
#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
/* Pin Connect Block */
#define PINSEL_BASE_ADDR 0xE002C000
#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
/* General Purpose Input/Output (GPIO) */
#define GPIO_BASE_ADDR 0xE0028000
#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
/* Fast I/O setup */
#define FIO_BASE_ADDR 0x3FFFC000
#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00))
#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01))
#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02))
#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03))
#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10))
#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11))
#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12))
#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13))
#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14))
#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15))
#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16))
#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17))
#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18))
#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19))
#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20))
#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C))
#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D))
#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E))
#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F))
#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20))
#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22))
#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23))
#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30))
#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x31))
#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32))
#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33))
#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34))
#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35))
#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36))
#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37))
#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38))
#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x39))
#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A))
#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B))
#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C))
#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3D))
#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E))
#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F))
/* System Control Block(SCB) modules include Memory Accelerator Module,
Phase Locked Loop, VPB divider, Power Control, External Interrupt,
Reset, and Code Security/Debugging */
#define SCB_BASE_ADDR 0xE01FC000
/* Memory Accelerator Module (MAM) */
#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040))
/* Phase Locked Loop (PLL) */
#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
/* PLL48 Registers */
#define PLL48CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A0))
#define PLL48CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A4))
#define PLL48STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A8))
#define PLL48FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0AC))
/* Power Control */
#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
/* VPB Divider */
#define VPBDIV (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100))
/* External Interrupts */
#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
/* Reset */
#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
/* System Controls and Status */
#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
/* Timer 0 */
#define TMR0_BASE_ADDR 0xE0004000
#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
/* Timer 1 */
#define TMR1_BASE_ADDR 0xE0008000
#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
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