unsigned char nrf24l01_get_arc_cnt()
{
	unsigned char data;
	
	nrf24l01_read_register(nrf24l01_OBSERVE_TX, &data, 1);
	
	return (data & nrf24l01_OBSERVE_TX_ARC_CNT);
}

//returns true if auto-ack is enabled on the pipe that is offset by rxpipenum
//unsigned char rxpipenum is the pipe number (zero to five) whose address is being
//	specified.  If an invalid address (greater than five) is supplied, the function
//  returns false.
bool nrf24l01_aa_enabled(unsigned char rxpipenum)
{
	unsigned char data;
	
	if(rxpipenum > 5)
		return false;
		
	nrf24l01_read_register(nrf24l01_EN_AA, &data, 1);
	
	return (data & (0x01 << rxpipenum));
}

//enables auto-ack is enabled on the pipe that is offset by rxpipenum
//unsigned char rxpipenum is the pipe number (zero to five) whose address is being
//	does nothing.
void nrf24l01_aa_enable(unsigned char rxpipenum)
{
	unsigned char data;
	
	if(rxpipenum > 5)
		return;
		
	nrf24l01_read_register(nrf24l01_EN_AA, &data, 1);
	
	if((data & (0x01 << rxpipenum)) != 0)
		return;
	
	data |= 0x01 << rxpipenum;
		
	nrf24l01_write_register(nrf24l01_EN_AA, &data, 1);
}

//disables auto-ack is enabled on the pipe that is offset by rxpipenum
//unsigned char rxpipenum is the pipe number (zero to five) whose address is being
//	does nothing.
void nrf24l01_aa_disable(unsigned char rxpipenum)
{
	unsigned char data;
	
	if(rxpipenum > 5)
		return;
		
	nrf24l01_read_register(nrf24l01_EN_AA, &data, 1);
	
	if((data & (0x01 << rxpipenum)) == 0)
		return;
	
	data &= ~(0x01 << rxpipenum);
		
	nrf24l01_write_register(nrf24l01_EN_AA, &data, 1);
}

//returns true if the pipe is enabled that is offset by rxpipenum
//unsigned char rxpipenum is the pipe number (zero to five) whose address is being
//	specified.  If an invalid address (greater than five) is supplied, the function
//  returns false.
bool nrf24l01_rx_pipe_enabled(unsigned char rxpipenum)
{
	unsigned char data;
	
	if((rxpipenum > 5))
		return false;
		
	nrf24l01_read_register(nrf24l01_EN_RXADDR, &data, 1);
	
	return (data & (0x01 << rxpipenum));
}

//enables the pipe that is offset by rxpipenum
//unsigned char rxpipenum is the pipe number (zero to five) whose address is being
//	specified.  If an invalid address (greater than five) is supplied, the function
//  does nothing.
void nrf24l01_rx_pipe_enable(unsigned char rxpipenum)
{
	unsigned char data;
	
	if(rxpipenum > 5)
		return;
		
	nrf24l01_read_register(nrf24l01_EN_RXADDR, &data, 1);
	
	if((data & (0x01 << rxpipenum)) != 0)
		return;
	
	data |= 0x01 << rxpipenum;
		
	nrf24l01_write_register(nrf24l01_EN_RXADDR, &data, 1);
}

//disables the pipe that is offset by rxpipenum
//unsigned char rxpipenum is the pipe number (zero to five) whose address is being
//	specified.  If an invalid address (greater than five) is supplied, the function
//  does nothing.
void nrf24l01_rx_pipe_disable(unsigned char rxpipenum)
{
	unsigned char data;
	
	if(rxpipenum > 5)
		return;
		
	nrf24l01_read_register(nrf24l01_EN_RXADDR, &data, 1);
	
	if((data & (0x01 << rxpipenum)) == 0)
		return;
	
	data &= ~(0x01 << rxpipenum);
		
	nrf24l01_write_register(nrf24l01_EN_RXADDR, &data, 1);
}

//returns the status of the CD register (true if carrier detect [CD] is
//  active, false if not)
bool nrf24l01_cd_active()
{
	unsigned char data;
	
	nrf24l01_read_register(nrf24l01_CD, &data, 1);
	
	return data;
}

//returns the value of the FIFO_STATUS register
unsigned char nrf24l01_get_fifo_status()
{
	unsigned char data;
	
	nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1);
	
	return data;
}

//return the value of the status register
unsigned char nrf24l01_get_status()
{
	return nrf24l01_nop();
}

//returns true if TX_REUSE bit in FIFO_STATUS register is set, false otherwise
bool nrf24l01_fifo_tx_reuse()
{
	unsigned char data;
	
	nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1);
	
	return (bool)(data & nrf24l01_FIFO_STATUS_TX_REUSE);
}

//returns true if TX_FULL bit in FIFO_STATUS register is set, false otherwise
bool nrf24l01_fifo_tx_full()
{
	unsigned char data;
	
	nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1);
	
	return (bool)(data & nrf24l01_FIFO_STATUS_TX_FULL);
}

//returns true if TX_EMPTY bit in FIFO_STATUS register is set, false otherwise
bool nrf24l01_fifo_tx_empty()
{
	unsigned char data;
	
	nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1);
	
	return (bool)(data & nrf24l01_FIFO_STATUS_TX_EMPTY);
}

//returns true if RX_FULL bit in FIFO_STATUS register is set, false otherwise
bool nrf24l01_fifo_rx_full()
{
	unsigned char data;
	
	nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1);
	
	return (bool)(data & nrf24l01_FIFO_STATUS_RX_FULL);
}

//returns true if RX_EMPTYE bit in FIFO_STATUS register is set, false otherwise
bool nrf24l01_fifo_rx_empty()
{
	unsigned char data;
	
	nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1);
	
	return (bool)(data & nrf24l01_FIFO_STATUS_RX_EMPTY);
}

//returns true if IRQ pin is low, false otherwise
bool nrf24l01_irq_pin_active()
{
	if((nrf24l01_IRQ_IOREGISTER & nrf24l01_IRQ_PINMASK) != 0)
		return false;
	else
		return true;
}

//returns true if RX_DR interrupt is active, false otherwise
bool nrf24l01_irq_rx_dr_active()
{
	return (nrf24l01_get_status() & nrf24l01_STATUS_RX_DR);
}

//returns true if TX_DS interrupt is active, false otherwise
bool nrf24l01_irq_tx_ds_active()
{
	return (nrf24l01_get_status() & nrf24l01_STATUS_TX_DS);
}

//returns true if MAX_RT interrupt is active, false otherwise
bool nrf24l01_irq_max_rt_active()
{
	return (nrf24l01_get_status() & nrf24l01_STATUS_MAX_RT);
}

//clear all interrupts in the status register
void nrf24l01_irq_clear_all()
{
	unsigned char data = nrf24l01_STATUS_RX_DR | nrf24l01_STATUS_TX_DS | nrf24l01_STATUS_MAX_RT;
	
	nrf24l01_write_register(nrf24l01_STATUS, &data, 1); 
}

//clears only the RX_DR interrupt
void nrf24l01_irq_clear_rx_dr()
{
	unsigned char data = nrf24l01_STATUS_RX_DR;
	
	nrf24l01_write_register(nrf24l01_STATUS, &data, 1); 
}

//clears only the TX_DS interrupt
void nrf24l01_irq_clear_tx_ds()
{
	unsigned char data = nrf24l01_STATUS_TX_DS;
	
	nrf24l01_write_register(nrf24l01_STATUS, &data, 1); 
}

//clears only the MAX_RT interrupt
void nrf24l01_irq_clear_max_rt()
{
	unsigned char data = nrf24l01_STATUS_MAX_RT;
	
	nrf24l01_write_register(nrf24l01_STATUS, &data, 1); 
}

//returns the current pipe in the 24L01's STATUS register
unsigned char nrf24l01_get_rx_pipe()
{
	return nrf24l01_get_rx_pipe_from_status(nrf24l01_get_status());
}

unsigned char nrf24l01_get_rx_pipe_from_status(unsigned char status)
{
	return ((status & 0xE) >> 1);
}

//flush both fifos and clear interrupts
void nrf24l01_clear_flush()
{
	nrf24l01_flush_rx();
	nrf24l01_flush_tx();
	nrf24l01_irq_clear_all();
}

//unsigned char * data must be at least 35 bytes long
void nrf24l01_get_all_registers(unsigned char * data)
{
	unsigned int outer;
	unsigned int inner;
	unsigned int dataloc = 0;
	unsigned char buffer[5];
	
	for(outer = 0; outer <= 0x17; outer++)
	{
		nrf24l01_read_register(outer, buffer, 5);
		
		for(inner = 0; inner < 5; inner++)
		{
			if(inner >= 1 && (outer != 0x0A && outer != 0x0B && outer != 0x10))
				break;
				
			data[dataloc] = buffer[inner];
			dataloc++;
		}
	}
}

//low-level spi send function for library use
//the user should not call this function directly, but rather use one of the 8 SPI data instructions
unsigned char nrf24l01_execute_command(unsigned char instruction, unsigned char * data, unsigned int len, bool copydata)
{
	unsigned char status;
	
	nrf24l01_clear_csn();

	status = instruction;
	nrf24l01_spi_send_read(&status, 1, true);
	nrf24l01_spi_send_read(data, len, copydata);
	
	nrf24l01_set_csn();		

	return status;
}

//low-level spi send function for library use
//the user should not call this function directly, but rather use one of the 8 SPI data instructions
void nrf24l01_spi_send_read(unsigned char * data, unsigned int len, bool copydata)
{
	unsigned int count;
	unsigned char tempbyte;

	for(count = 0; count < len; count++)
	{
		if(copydata != false)
			data[count] = spi_send_read_byte(data[count]);
		else
		{
			tempbyte = data[count];
			spi_send_read_byte(tempbyte);
		}
	}
}