}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_CleanDCacheMVA
//* \brief Clean DCache single entry (using MVA)
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_CleanDCacheMVA(unsigned int mva)
{
 	__asm("MCR p15, 0, (mva & 0xFFFFFFE0), c7, c10, 1");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_CleanInvalidateDCacheMVA
//* \brief Clean and Invalidate DCache single entry (using MVA)
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_CleanInvalidateDCacheMVA(unsigned int mva)
{
 	__asm("MCR p15, 0, (mva & 0xFFFFFFE0), c7, c14, 1");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_CleanDCacheIDX
//* \brief Clean DCache single entry (using index)
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_CleanDCacheIDX(unsigned int index)
{
 	__asm("MCR p15, 0, (index & 0xFC0000E0), c7, c10, 2");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_CleanInvalidateDCacheIDX
//* \brief Clean and Invalidate DCache single entry (using index)
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_CleanInvalidateDCacheIDX(unsigned int index)
{
 	__asm("MCR p15, 0, (index & 0xFC0000E0), c7, c14, 2");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_DrainWriteBuffer
//* \brief Drain Write Buffer
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_DrainWriteBuffer()
{
	register unsigned int sbz = 0;
 	__asm("MCR p15, 0, sbz, c7, c10, 4");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WaitForInterrupt
//* \brief Wait for interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WaitForInterrupt()
{
	register unsigned int sbz = 0;
	__asm("MCR p15, 0, sbz, c7, c0, 4");
}

// ****************************************************************************
// CP15 Register 8
// 	Read: Unpredictable
//	Write: TLB operations

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateIDTLB
//* \brief Invalidate TLB(s)
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_InvalidateIDTLB()
{
	register unsigned int sbz = 0;
 	__asm("MCR p15, 0, sbz, c8, c7, 0");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateITLB
//* \brief Invalidate I TLB
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_InvalidateITLB()
{
	register unsigned int sbz = 0;
 	__asm("MCR p15, 0, sbz, c8, c5, 0");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateITLBMVA
//* \brief Invalidate I TLB single entry (using MVA)
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_InvalidateITLBMVA(unsigned int mva)
{
 	__asm("MCR p15, 0, (mva & 0xFFFFFE00), c8, c5, 1");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateDTLB
//* \brief Invalidate D TLB
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_InvalidateDTLB()
{
	register unsigned int sbz = 0;
 	__asm("MCR p15, 0, sbz, c8, c6, 0");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateDTLBMVA
//* \brief Invalidate D TLB single entry (using MVA)
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_InvalidateDTLBMVA(unsigned int mva)
{
 	__asm("MCR p15, 0, (mva & 0xFFFFFE00), c8, c6, 1");
}


// ****************************************************************************
// CP15 Register 9
// 	Read: Cache lockdown
//	Write: Cache lockdown

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadDCacheLockdown
//* \brief Read D Cache lockdown
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadDCacheLockdown()
{
	register unsigned int index;
 	__asm("MRC p15, 0, index, c9, c0, 0");
    return index;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteDCacheLockdown
//* \brief Write D Cache lockdown
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteDCacheLockdown(
	unsigned int index)
{
	__asm("MCR p15, 0, index, c9, c0, 0");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadICacheLockdown
//* \brief Read I Cache lockdown
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadICacheLockdown()
{
	register unsigned int index;
	__asm("MRC p15, 0, index, c9, c0, 1");
	return index;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteICacheLockdown
//* \brief Write I Cache lockdown
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteICacheLockdown(
	unsigned int index)
{
	__asm("MCR p15, 0, index, c9, c0, 1");
}

// ****************************************************************************
// CP15 Register 10
// 	Read: TLB lockdown
//	Write: TLB lockdown

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadDTLBLockdown
//* \brief Read D TLB lockdown
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadDTLBLockdown()
{
	register unsigned int lockdown;
 	__asm("MRC p15, 0, lockdown, c10, c0, 0");
    return lockdown;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteDTLBLockdown
//* \brief Write D TLB lockdown
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteDTLBLockdown(
	unsigned int lockdown)
{
	__asm("MCR p15, 0, lockdown, c10, c0, 0");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadITLBLockdown
//* \brief Read I TLB lockdown
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadITLBLockdown()
{
	register unsigned int lockdown;
	__asm("MRC p15, 0, lockdown, c10, c0, 1");
	return lockdown;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteITLBLockdown
//* \brief Write I TLB lockdown
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteITLBLockdown(
	unsigned int lockdown)
{
	__asm("MCR p15, 0, lockdown, c10, c0, 1");
}

// ****************************************************************************
// CP15 Register 13
// 	Read: Read FCSE PID
//	Write: Write FCSE PID

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadFCSEPID
//* \brief Read FCSE PID
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadFCSEPID()
{
	register unsigned int pid;
 	__asm("MRC p15, 0, pid, c13, c0, 0");
 	return pid;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteFCSEPID
//* \brief Write FCSE PID
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteFCSEPID(unsigned int pid)
{
 	__asm("MCR p15, 0, (pid & 0xFF000000), c13, c0, 0");
}