?? stm32f10x_tim.h
字號:
((LENGTH) == TIM_DMABurstLength_13Bytes) || \
((LENGTH) == TIM_DMABurstLength_14Bytes) || \
((LENGTH) == TIM_DMABurstLength_15Bytes) || \
((LENGTH) == TIM_DMABurstLength_16Bytes) || \
((LENGTH) == TIM_DMABurstLength_17Bytes) || \
((LENGTH) == TIM_DMABurstLength_18Bytes))
/* TIM DMA sources ---------------------------------------------------------*/
#define TIM_DMA_Update ((u16)0x0100)
#define TIM_DMA_CC1 ((u16)0x0200)
#define TIM_DMA_CC2 ((u16)0x0400)
#define TIM_DMA_CC3 ((u16)0x0800)
#define TIM_DMA_CC4 ((u16)0x1000)
#define TIM_DMA_COM ((u16)0x2000)
#define TIM_DMA_Trigger ((u16)0x4000)
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
(((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
(((SOURCE) & (u16)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
(((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
(((SOURCE) & (u16)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
/* TIM External Trigger Prescaler ------------------------------------------*/
#define TIM_ExtTRGPSC_OFF ((u16)0x0000)
#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000)
#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)
#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
/* TIM Internal Trigger Selection ------------------------------------------*/
#define TIM_TS_ITR0 ((u16)0x0000)
#define TIM_TS_ITR1 ((u16)0x0010)
#define TIM_TS_ITR2 ((u16)0x0020)
#define TIM_TS_ITR3 ((u16)0x0030)
#define TIM_TS_TI1F_ED ((u16)0x0040)
#define TIM_TS_TI1FP1 ((u16)0x0050)
#define TIM_TS_TI2FP2 ((u16)0x0060)
#define TIM_TS_ETRF ((u16)0x0070)
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
((SELECTION) == TIM_TS_ITR1) || \
((SELECTION) == TIM_TS_ITR2) || \
((SELECTION) == TIM_TS_ITR3) || \
((SELECTION) == TIM_TS_TI1F_ED) || \
((SELECTION) == TIM_TS_TI1FP1) || \
((SELECTION) == TIM_TS_TI2FP2) || \
((SELECTION) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
((SELECTION) == TIM_TS_ITR1) || \
((SELECTION) == TIM_TS_ITR2) || \
((SELECTION) == TIM_TS_ITR3))
/* TIM TIx External Clock Source -------------------------------------------*/
#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)
#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)
#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
/* TIM External Trigger Polarity -------------------------------------------*/
#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)
#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
/* TIM Prescaler Reload Mode -----------------------------------------------*/
#define TIM_PSCReloadMode_Update ((u16)0x0000)
#define TIM_PSCReloadMode_Immediate ((u16)0x0001)
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
((RELOAD) == TIM_PSCReloadMode_Immediate))
/* TIM Forced Action -------------------------------------------------------*/
#define TIM_ForcedAction_Active ((u16)0x0050)
#define TIM_ForcedAction_InActive ((u16)0x0040)
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
((ACTION) == TIM_ForcedAction_InActive))
/* TIM Encoder Mode --------------------------------------------------------*/
#define TIM_EncoderMode_TI1 ((u16)0x0001)
#define TIM_EncoderMode_TI2 ((u16)0x0002)
#define TIM_EncoderMode_TI12 ((u16)0x0003)
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
((MODE) == TIM_EncoderMode_TI2) || \
((MODE) == TIM_EncoderMode_TI12))
/* TIM Event Source --------------------------------------------------------*/
#define TIM_EventSource_Update ((u16)0x0001)
#define TIM_EventSource_CC1 ((u16)0x0002)
#define TIM_EventSource_CC2 ((u16)0x0004)
#define TIM_EventSource_CC3 ((u16)0x0008)
#define TIM_EventSource_CC4 ((u16)0x0010)
#define TIM_EventSource_COM ((u16)0x0020)
#define TIM_EventSource_Trigger ((u16)0x0040)
#define TIM_EventSource_Break ((u16)0x0080)
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (u16)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
(((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
(((EVENT) & (u16)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
(((EVENT) & (u16)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
(((EVENT) & (u16)0xFFFE) == 0x0000) && ((EVENT) != 0x0000)))
/* TIM Update Source --------------------------------------------------------*/
#define TIM_UpdateSource_Global ((u16)0x0000)
#define TIM_UpdateSource_Regular ((u16)0x0001)
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
((SOURCE) == TIM_UpdateSource_Regular))
/* TIM Ouput Compare Preload State ------------------------------------------*/
#define TIM_OCPreload_Enable ((u16)0x0008)
#define TIM_OCPreload_Disable ((u16)0x0000)
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
((STATE) == TIM_OCPreload_Disable))
/* TIM Ouput Compare Fast State ---------------------------------------------*/
#define TIM_OCFast_Enable ((u16)0x0004)
#define TIM_OCFast_Disable ((u16)0x0000)
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
((STATE) == TIM_OCFast_Disable))
/* TIM Ouput Compare Clear State --------------------------------------------*/
#define TIM_OCClear_Enable ((u16)0x0080)
#define TIM_OCClear_Disable ((u16)0x0000)
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
((STATE) == TIM_OCClear_Disable))
/* TIM Trigger Output Source ------------------------------------------------*/
#define TIM_TRGOSource_Reset ((u16)0x0000)
#define TIM_TRGOSource_Enable ((u16)0x0010)
#define TIM_TRGOSource_Update ((u16)0x0020)
#define TIM_TRGOSource_OC1 ((u16)0x0030)
#define TIM_TRGOSource_OC1Ref ((u16)0x0040)
#define TIM_TRGOSource_OC2Ref ((u16)0x0050)
#define TIM_TRGOSource_OC3Ref ((u16)0x0060)
#define TIM_TRGOSource_OC4Ref ((u16)0x0070)
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
((SOURCE) == TIM_TRGOSource_Enable) || \
((SOURCE) == TIM_TRGOSource_Update) || \
((SOURCE) == TIM_TRGOSource_OC1) || \
((SOURCE) == TIM_TRGOSource_OC1Ref) || \
((SOURCE) == TIM_TRGOSource_OC2Ref) || \
((SOURCE) == TIM_TRGOSource_OC3Ref) || \
((SOURCE) == TIM_TRGOSource_OC4Ref))
#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_Reset)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_Enable)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_Update)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_OC1)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_OC1Ref)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_OC2Ref)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
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