// SCL is high and allows Timer 3 to count when SCL goes low. Timer 3 should
                            // be programmed to generate interrupts at 25 ms, and the Timer 3 ISR should
                            // reset SMBus comm.
#define BM_SMBFTE   0x04    // SMBus Free Timeout Detection Enable. When set to 1, the bus will be 
                            // considered free if SCL and SDA remain high for more than 10 SMBus clock
                            // source periods.
#define BM_SMBCS1   0x02    // SMBus Clock Source Selection.
#define BM_SMBCS0   0x01    //      00: Timer 0 Overflow
                            //      01: Timer 1 Overflow
                            //      10: Timer 2 High Byte Overflow
                            //      11: Timer 2 Low Byte Overflow

#define TIMER_0_OVERFLOW            0
#define TIMER_1_OVERFLOW            1
#define TIMER_2_HIGH_BYTE_OVERFLOW  2
#define TIMER_2_LOW_BYTE_OVERFLOW   3

// SMB0CN - SMBus Control Register
#define BM_MASTER   0x80    // SMBus Master/Slave Indicator
                            //      0: SMBus operating in Slave Mode
                            //      1: SMBus operating in Master Mode.
#define BM_TXMODE   0x40    // SMBus Transmit Mode Indicator. This read-only bit indicates when the 
                            // SMBus is operating as a transmitter.
                            //      0: SMBus in Receiver Mode
                            //      1: SMBus in Transmitter Mode.
#define BM_STA      0x20    //  SMBus Start Flag.
                            //      Write:
                            //          0: No Start generated
                            //          1: When operating as a master, a START condition is transmitted 
                            //             if the bus is free (If the bus is not free, the START is
                            //             transmitted after a STOP is received or a timeout is detected).
                            //             If STA is set by SW  as an active Master, a repeated START
                            //             will be generated after the next ACK cycle
                            //      Read:
                            //          0: No Start or repeated Start detected
                            //          1: Start or repeated Start detected.
#define BM_STO      0x10    // SMBus Stop Flag
                            //      Write:
                            //          0: No STOP condition is transmitted
                            //          1: Setting STO to logic 1 causes a STOP condition to be 
                            //             transmitted after the next ACK cycle. When the STOP condition 
                            //             is generated, HW clears STO. If both STA and STO are set, a
                            //             STOP condition is transmitted followed by a START condition
                            //      Read:
                            //          0: No Stop condition detected
                            //          1: Stop condition detected (Slave Mode) or pending (Master Mode)
#define BM_ACKRQ    0x08    // SMBus Acknowledge Request. This read-only bit is set when the SMBus has
                            // received a byte and needs the ACK bit to be written with the correct ACK
                            // response value.
#define BM_ARBLOST  0x04    // SMBus Arbitration Lost Indicator. This read-only bit is set when the
                            // SMBus loses arbitration while operating as a transmitter. A lost
                            // arbitration while a slave indicates a bus error condition.
#define BM_ACK      0x02    // SMBus Acknowledge Flag. This bit defines the out-going ACK level and
                            // records incoming ACK levels. It should be written each time a byte is
                            // received (when ACKRQ=1), or read after each byte is transmitted
                            //      0: A "not acknowledge" has been received (if in Transmitter Mode)
                            //         OR will be transmitted (if in Receiver Mode)
                            //      1: An "acknowledge" has been received (if in Transmitter Mode) OR
                            //         will be transmitted (if in Receiver Mode).
#define BM_SI       0x01    // SMBus Interrupt Flag. Must be cleared by SW. While SI is set, SCL is
                            // held low and the SMBus is stalled.
//------------------------------------------------------------------------------------------------------


//------------------------------------------------------------------------------------------------------
// Crossbar

// XBR0 - Port I/O Crossbar Register 0
#define BM_CP1AE        0x80    // Comparator1 Asynchronous Output Enable
#define BM_CP1E         0x40    // Comparator1 Output Enable
#define BM_CP0AE        0x20    // Comparator0 Asynchronous Output Enable
#define BM_CP0E         0x10    // Comparator0 Output Enable
#define BM_SYSCKE       0x08    // SYSCLK Output Enable
#define BM_SMB0E        0x04    // SMBus I/O Enable
#define BM_SPI0E        0x02    // SPI I/O Enable
#define BM_URT0E        0x01    // UART I/O Output Enable

// XBR1 - Port I/O Crossbar Register 1
#define BM_WEAKPUD      0x80    // Port I/O Weak Pull-up Disable:
                                //      0: Weak Pull-ups enabled (except for Ports whose I/O are
                                //         configured as analog input or push-pull output).
                                //      1: Weak Pull-ups disabled.
#define BM_XBAR         0x40    // Crossbar Enable
#define BM_T1E          0x20    // T1 Enable
#define BM_T0E          0x10    // T0 Enable
#define BM_ECIE         0x08    // PCA0 External Counter Input Enable
#define BM_PCA0ME_0     0x00    //      000: All PCA I/O unavailable at Port pins.
#define BM_PCA0ME_1     0x01    //      001: CEX0 routed to Port pin.
#define BM_PCA0ME_2     0x02    //      010: CEX0, CEX1 routed to Port pins.
#define BM_PCA0ME_3     0x03    //      011: CEX0, CEX1, CEX2 routed to Port pins.
#define BM_PCA0ME_4     0x04    //      100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
#define BM_PCA0ME_5     0x05    //      101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
#define BM_PCA0ME_6     0x06    //      110: Reserved.
#define BM_PCA0ME_7     0x07    //      111: Reserved.
//------------------------------------------------------------------------------------------------------


//------------------------------------------------------------------------------------------------------
// SPI Special Function Registers

// SPI0CFG - SPI0 Configuration Register
#define BM_SPIBSY   0x80    // SPI Busy: Set to 1 when a SPI transfer is in progress
#define BM_MSTEN    0x40    // Master Mode Enable: Active High
#define BM_CKPHA    0x20    // SPI0 Clock Phase:
                            //      0: Data centered on first edge of SCK period
                            //      1: Data centered on second edge of SCK period.
#define BM_CKPOL    0x10    // SPI0 Clock Polarity:
                            //      0: SCK low in Idle State
                            //      1: SCK high in Idle State
#define BM_SLVSEL   0x08    // Slave Selected: Set to 1 whenever the NSS pin is low indicating SPI0 is
#define BM_NSSIN    0x04    // the NSS Instantaneous Pin Input
                            // selected slave
#define BM_SRMT     0x02    // Shift Register Empty: Valid in Slave Mode
#define BM_RXBMT    0x01    // Receive Buffer Empty: Valid in Slave Mode

// SPI0CN - SPI0 Control Register
#define BM_SPIF     0x80    // SPI0 Interrupt Flag: Set to 1 at the end of a data transfer. Cleard by SW
#define BM_WCOL     0x40    // Write Collision Flag: Set to 1 to indicate a write to the SPI0 data register 
                            // was attempted while a data transfer was in progress. Cleared by software.
#define BM_MODF     0x20    // Mode Fault Flag: Set when a master mode collision is detected. Cleared by SW
#define BM_RXOVRN   0x10    // Receive Overrun Flag: Set to 1 when the receive buffer still holds unread
                            // data from a previous transfer and the last bit of the current transfer is
                            // shifted into the SPI0 shift register. Cleared by SW.
#define BM_NSSMD1   0x08    // Slave Select Mode
#define BM_NSSMD0   0x04    // Slave Select Mode
                            //      00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a
                            //          port pin.
                            //      01: 4-Wire Slave or Multi-Master Mode. NSS is always an input to the
                            //          device.
                            //      1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from
                            //          the device and will assume  the value of NSSMD0
#define BM_TXBMT    0x02    // Transmit Buffer Empty: Set to 0 when new data has been written to the
                            // transmit buffer. When data in the transmit buffer is transferred to the SPI
                            // shift register, this bit will be set to 1, indicating that it is safe to
                            // transmit buffer.
#define BM_SPIEN    0x01    // SPI0 Enable: Active high
//------------------------------------------------------------------------------------------------------


//------------------------------------------------------------------------------------------------------
// OSCICN - Internal Oscillator Control Register
#define BM_IOSCEN       0x80    // Internal Oscillator Enable Bit: Active High
#define BM_IFRDY        0x40    // Internal Oscillator Frequency Ready Flag:
                                //      0: Internal Oscillator is not running at programmed frequency.
                                //      1: Internal Oscillator is running at programmed frequency.
#define BM_SUSPEND      0x20    // Force Suspend: SuspendWriting a