?? hour.rpt
字號:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 11/ 96( 11%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\vhdl\digclock\hour.rpt
hour
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: c:\vhdl\digclock\hour.rpt
hour
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 reset
Device-Specific Information: c:\vhdl\digclock\hour.rpt
hour
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is 'daout0'
-- Equation name is 'daout0', type is output
daout0 = da10~116;
-- Node name is 'daout1'
-- Equation name is 'daout1', type is output
daout1 = da11~116;
-- Node name is 'daout2'
-- Equation name is 'daout2', type is output
daout2 = da12~116;
-- Node name is 'daout3'
-- Equation name is 'daout3', type is output
daout3 = da13~116;
-- Node name is 'daout4'
-- Equation name is 'daout4', type is output
daout4 = da20~118;
-- Node name is 'daout5'
-- Equation name is 'daout5', type is output
daout5 = da21~118;
-- Node name is 'daout6'
-- Equation name is 'daout6', type is output
daout6 = da22~118;
-- Node name is 'daout7'
-- Equation name is 'daout7', type is output
daout7 = da23~118;
-- Node name is ':78' = 'da10~116'
-- Equation name is 'da10~116', location is LC7_B24, type is buried.
da10~116 = DFFE( _EQ001, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ001 = !da10~116 & _LC3_B24 & !_LC4_B21
# !da10~116 & !_LC4_B21 & _LC7_B9;
-- Node name is ':77' = 'da11~116'
-- Equation name is 'da11~116', location is LC1_B24, type is buried.
da11~116 = DFFE( _EQ002, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ002 = !da10~116 & da11~116 & !da13~116 & !_LC8_B24
# da10~116 & !da11~116 & !da13~116 & !_LC8_B24;
-- Node name is ':76' = 'da12~116'
-- Equation name is 'da12~116', location is LC2_B24, type is buried.
da12~116 = DFFE( _EQ003, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ003 = da12~116 & !_LC5_B24 & !_LC6_B24 & _LC7_B9
# !da12~116 & !_LC5_B24 & _LC6_B24 & _LC7_B9;
-- Node name is ':75' = 'da13~116'
-- Equation name is 'da13~116', location is LC5_B21, type is buried.
da13~116 = DFFE( _EQ004, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ004 = !_LC4_B24 & _LC5_B24 & _LC7_B9;
-- Node name is ':74' = 'da20~118'
-- Equation name is 'da20~118', location is LC1_B9, type is buried.
da20~118 = DFFE( _EQ005, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ005 = da20~118 & _LC3_B24 & !_LC4_B21
# !da20~118 & _LC3_B24 & _LC4_B21
# da20~118 & !_LC4_B21 & _LC7_B9
# !da20~118 & _LC4_B21 & _LC7_B9;
-- Node name is ':73' = 'da21~118'
-- Equation name is 'da21~118', location is LC6_B9, type is buried.
da21~118 = DFFE( _EQ006, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ006 = !da20~118 & da21~118 & _LC3_B24
# da20~118 & !da21~118 & _LC3_B24 & _LC4_B21
# da21~118 & _LC3_B24 & !_LC4_B21;
-- Node name is ':72' = 'da22~118'
-- Equation name is 'da22~118', location is LC8_B9, type is buried.
da22~118 = DFFE( _EQ007, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ007 = da22~118 & _LC3_B24 & !_LC5_B9
# !da22~118 & _LC3_B24 & _LC4_B21 & _LC5_B9
# da22~118 & _LC3_B24 & !_LC4_B21;
-- Node name is ':71' = 'da23~118'
-- Equation name is 'da23~118', location is LC2_B9, type is buried.
da23~118 = DFFE( _EQ008, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ008 = da23~118 & _LC3_B24 & !_LC4_B9
# !da23~118 & _LC3_B24 & _LC4_B9 & _LC4_B21
# da23~118 & _LC3_B24 & !_LC4_B21;
-- Node name is '|LPM_ADD_SUB:103|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = LCELL( _EQ009);
_EQ009 = da10~116 & da11~116;
-- Node name is '|LPM_ADD_SUB:103|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ010);
_EQ010 = !da12~116 & da13~116
# da13~116 & !_LC6_B24
# da12~116 & !da13~116 & _LC6_B24;
-- Node name is '|LPM_ADD_SUB:125|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ011);
_EQ011 = da20~118 & da21~118;
-- Node name is '|LPM_ADD_SUB:125|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = LCELL( _EQ012);
_EQ012 = da20~118 & da21~118 & da22~118;
-- Node name is ':106'
-- Equation name is '_LC4_B21', type is buried
!_LC4_B21 = _LC4_B21~NOT;
_LC4_B21~NOT = LCELL( _EQ013);
_EQ013 = !_LC4_B24
# !_LC5_B24;
-- Node name is ':109'
-- Equation name is '_LC4_B24', type is buried
!_LC4_B24 = _LC4_B24~NOT;
_LC4_B24~NOT = LCELL( _EQ014);
_EQ014 = da10~116 & da11~116 & da12~116
# !da10~116 & !da11~116 & !da12~116;
-- Node name is '~182~1'
-- Equation name is '~182~1', location is LC3_B9, type is buried.
-- synthesized logic cell
_LC3_B9 = LCELL( _EQ015);
_EQ015 = da20~118 & da21~118 & da22~118 & _LC4_B21
# !da20~118 & !da21~118 & !da22~118
# !da21~118 & !da22~118 & !_LC4_B21;
-- Node name is ':182'
-- Equation name is '_LC7_B9', type is buried
_LC7_B9 = LCELL( _EQ016);
_EQ016 = !da23~118 & _LC3_B9 & !_LC4_B9
# !da23~118 & _LC3_B9 & !_LC4_B21
# da23~118 & _LC3_B9 & _LC4_B9 & _LC4_B21;
-- Node name is ':200'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ017);
_EQ017 = da12~116 & _LC4_B24 & _LC6_B24
# da12~116 & !_LC5_B24 & _LC6_B24
# !da12~116 & _LC4_B24 & !_LC6_B24
# !da12~116 & !_LC5_B24 & !_LC6_B24
# _LC4_B24 & _LC5_B24;
-- Node name is ':216'
-- Equation name is '_LC8_B24', type is buried
!_LC8_B24 = _LC8_B24~NOT;
_LC8_B24~NOT = LCELL( _EQ018);
_EQ018 = _LC3_B24
# _LC7_B9;
Project Information c:\vhdl\digclock\hour.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,651K
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