?? digclock.rpt
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Project Information h:\vhdl1\digclock\digclock.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 07/14/2008 10:14:59
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
digclock EP1K30QC208-2 6 21 0 0 0 % 131 7 %
User Pins: 6 21 0
Project Information h:\vhdl1\digclock\digclock.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
digclock@80 ckdsp
digclock@79 clk
digclock@183 clkspk
digclock@17 daout0
digclock@16 daout1
digclock@15 daout2
digclock@14 daout3
digclock@13 daout4
digclock@12 daout5
digclock@11 daout6
digclock@10 daout7
digclock@19 lamp0
digclock@24 lamp1
digclock@25 lamp2
digclock@26 lamp3
digclock@27 lamp4
digclock@28 lamp5
digclock@29 lamp6
digclock@30 lamp7
digclock@31 lamp8
digclock@45 reset
digclock@7 sel0
digclock@8 sel1
digclock@9 sel2
digclock@46 sethour
digclock@47 setmin
digclock@68 speak
Project Information h:\vhdl1\digclock\digclock.rpt
** FILE HIERARCHY **
|alert:1|
|deled:2|
|hour:3|
|hour:3|lpm_add_sub:103|
|hour:3|lpm_add_sub:103|addcore:adder|
|hour:3|lpm_add_sub:103|altshift:result_ext_latency_ffs|
|hour:3|lpm_add_sub:103|altshift:carry_ext_latency_ffs|
|hour:3|lpm_add_sub:103|altshift:oflow_ext_latency_ffs|
|hour:3|lpm_add_sub:125|
|hour:3|lpm_add_sub:125|addcore:adder|
|hour:3|lpm_add_sub:125|altshift:result_ext_latency_ffs|
|hour:3|lpm_add_sub:125|altshift:carry_ext_latency_ffs|
|hour:3|lpm_add_sub:125|altshift:oflow_ext_latency_ffs|
|minute:4|
|minute:4|lpm_add_sub:103|
|minute:4|lpm_add_sub:103|addcore:adder|
|minute:4|lpm_add_sub:103|altshift:result_ext_latency_ffs|
|minute:4|lpm_add_sub:103|altshift:carry_ext_latency_ffs|
|minute:4|lpm_add_sub:103|altshift:oflow_ext_latency_ffs|
|minute:4|lpm_add_sub:134|
|minute:4|lpm_add_sub:134|addcore:adder|
|minute:4|lpm_add_sub:134|altshift:result_ext_latency_ffs|
|minute:4|lpm_add_sub:134|altshift:carry_ext_latency_ffs|
|minute:4|lpm_add_sub:134|altshift:oflow_ext_latency_ffs|
|second:5|
|second:5|lpm_add_sub:103|
|second:5|lpm_add_sub:103|addcore:adder|
|second:5|lpm_add_sub:103|altshift:result_ext_latency_ffs|
|second:5|lpm_add_sub:103|altshift:carry_ext_latency_ffs|
|second:5|lpm_add_sub:103|altshift:oflow_ext_latency_ffs|
|second:5|lpm_add_sub:134|
|second:5|lpm_add_sub:134|addcore:adder|
|second:5|lpm_add_sub:134|altshift:result_ext_latency_ffs|
|second:5|lpm_add_sub:134|altshift:carry_ext_latency_ffs|
|second:5|lpm_add_sub:134|altshift:oflow_ext_latency_ffs|
|seltime:6|
|seltime:6|lpm_add_sub:121|
|seltime:6|lpm_add_sub:121|addcore:adder|
|seltime:6|lpm_add_sub:121|altshift:result_ext_latency_ffs|
|seltime:6|lpm_add_sub:121|altshift:carry_ext_latency_ffs|
|seltime:6|lpm_add_sub:121|altshift:oflow_ext_latency_ffs|
Device-Specific Information: h:\vhdl1\digclock\digclock.rpt
digclock
***** Logic for device 'digclock' compiled without errors.
Device: EP1K30QC208-2
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S V S S S S S S S S S S S S S V c S S S S S S S S S S S S S S S S S S S S S
E E E E E E E C E E E E E E V E E E E E E E C l E E V E E E E E E E E E E E V E E E E E E E E
R R R R R R R C R R R R R R C R R R R R R R C k R R C R R R R R R R R R R R C R R R R R R R R
V V V V V V V I V V V V V V C V V V V V G V V I G s G G V V C V V V V V V G V V V V V C V V V V V V V V
E E E E E E E N E E E E E E I E E E E E N E E N N p N N E E I E E E E E E N E E E E E I E E E E E E E E
D D D D D D D T D D D D D D O D D D D D D D D T D k D D D D O D D D D D D D D D D D D O D D D D D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
sel0 | 7 150 | RESERVED
sel1 | 8 149 | RESERVED
sel2 | 9 148 | RESERVED
daout7 | 10 147 | RESERVED
daout6 | 11 146 | VCCIO
daout5 | 12 145 | GND
daout4 | 13 144 | RESERVED
daout3 | 14 143 | RESERVED
daout2 | 15 142 | RESERVED
daout1 | 16 141 | RESERVED
daout0 | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
lamp0 | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | RESERVED
GND | 23 134 | RESERVED
lamp1 | 24 133 | RESERVED
lamp2 | 25 132 | RESERVED
lamp3 | 26 131 | RESERVED
lamp4 | 27 EP1K30QC208-2 130 | VCCINT
lamp5 | 28 129 | GND
lamp6 | 29 128 | RESERVED
lamp7 | 30 127 | RESERVED
lamp8 | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
RESERVED | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
reset | 45 112 | RESERVED
sethour | 46 111 | RESERVED
setmin | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R s R R R V R R R G V G c c G G R V R R R R R R V R R R R R R V R R R R R R
E E E E E E N E E E E E E C E p E E E C E E E N C N l k N N E C E E E E E E C E E E E E E C E E E E E E
S S S S S S D S S S S S S C S e S S S C S S S D C D k d D D S C S S S S S S C S S S S S S C S S S S S S
E E E E E E E E E E E E I E a E E E I E E E _ s _ E I E E E E E E I E E E E E E I E E E E E E
R R R R R R R R R R R R O R k R R R N R R R C p C R O R R R R R R N R R R R R R O R R R R R R
V V V V V V V V V V V V V V V V T V V V K K V V V V V V V T V V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E L L E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D K K D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: h:\vhdl1\digclock\digclock.rpt
digclock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
C20 8/ 8(100%) 6/ 8( 75%) 5/ 8( 62%) 1/2 1/2 2/22( 9%)
C21 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 17/22( 77%)
C22 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 3/22( 13%)
C24 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 6/22( 27%)
C26 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
C28 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 5/22( 22%)
C29 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
C30 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
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