library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minute is
port(reset,clk,sethour:in std_logic;
	enhour:out std_logic;--進位
	daout:out std_logic_vector(7 downto 0));
end minute;
architecture behave of minute is
begin
process(reset,clk,sethour)
variable da1:std_logic_vector(3 downto 0);
variable da2:std_logic_vector(3 downto 0);
begin
if(reset='0') then da1:="0000";da2:="0000";enhour<='0';
else
	if(clk'event and clk='1') then da1:=da1+1;
		if(da1>"1001") then da2:=da2+1;da1:="0000";
				if(da2>"0101") then enhour<='1';da1:="0000";da2:="0000";
				else enhour<='0';
				end if;
		end if;
		if(sethour='1') then enhour<='1';
		end if;
	end if;
end if;
daout(7 downto 4)<=da2;
daout(3 downto 0)<=da1;
end process;
end behave;