?? s12_register.h
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UINT8 :1; /*not used */
UINT8 psel1 :1; /*highest priority interrupt select bits */
UINT8 psel2 :1;
UINT8 psel3 :1;
UINT8 psel4 :1;
UINT8 psel5 :1;
UINT8 psel6 :1;
UINT8 psel7 :1;
}bit;
}tHPRIO;
typedef union uBKPCT0
{
UINT8 byte;
struct
{
UINT8 :4; /*not used */
UINT8 bktag :1;
UINT8 bkbdm :1;
UINT8 bkfull :1;
UINT8 bken :1; /*breakpoint mode enable */
}bit;
}tBKPCT0;
typedef union uBKPCT1
{
UINT8 byte;
struct
{
UINT8 bk1rw :1; /* */
UINT8 bk1rwe :1; /* */
UINT8 bk0rw :1; /* */
UINT8 bk0rwe :1; /* */
UINT8 bk1mbl :1; /* */
UINT8 bk1mbh :1; /* */
UINT8 bk0mbl :1; /* */
UINT8 bk0mbh :1; /* */
}bit;
}tBKPCT1;
typedef union uBKP0X
{
UINT8 byte;
struct
{
UINT8 bk0v :6; /* */
UINT8 :2; /*not used */
}bit;
}tBKP0X;
typedef union uBKP0
{
UINT16 word;
struct
{
UINT8 high;
UINT8 low;
}byte;
}tBKP0;
typedef union uBKP1X
{
UINT8 byte;
struct
{
UINT8 bk1v :6; /* */
UINT8 :2; /*not used */
}bit;
}tBKP1X;
typedef union uBKP1
{
UINT16 word;
struct
{
UINT8 high;
UINT8 low;
}byte;
}tBKP1;
typedef union uPPAGE
{
UINT8 byte;
struct
{
UINT8 pix :6; /*active page bits */
UINT8 :2; /* not used */
}bit;
}tPPAGE;
typedef union uPORTK
{
UINT8 byte;
struct
{
UINT8 ptk0 :1; /*i/o port pins */
UINT8 ptk1 :1;
UINT8 ptk2 :1;
UINT8 ptk3 :1;
UINT8 ptk4 :1;
UINT8 ptk5 :1;
UINT8 ptk6 :1;
UINT8 ptk7 :1;
}bit;
}tPORTK;
typedef union uDDRK
{
UINT8 byte;
struct
{
UINT8 ddrk0 :1; /*data direction bits (0:input;1:output) */
UINT8 ddrk1 :1;
UINT8 ddrk2 :1;
UINT8 ddrk3 :1;
UINT8 ddrk4 :1;
UINT8 ddrk5 :1;
UINT8 ddrk6 :1;
UINT8 ddrk7 :1;
}bit;
}tDDRK;
typedef struct /*port and internal resource control */
{
volatile tPORTA porta; /*port A data register */
volatile tPORTB portb; /*port B data register */
tDDRA ddra; /*port A data direction register */
tDDRB ddrb; /*port B data direction register */
UINT8 rsv1[4];/*reserved (maintaining memory map) */
volatile tPORTE porte; /*port E data register */
tDDRE ddre; /*port E data direction register */
tPEAR pear; /*port E assignment register */
tMODE mode; /*mode register */
tPUCR pucr; /*pull-up control register */
tRDRIV rdriv; /*reduced drive register */
tEBICTL ebictl; /*external bus control */
UINT8 rsv2; /*reserved (maintaining memory map) */
tINITRM initrm; /*initialise internal ram position */
tINITRG initrg; /*initialise internal register position */
tINITEE initee; /*initialise internal eeprom position */
tMISC misc; /*miscellaneous system control register */
UINT8 rsv3; /*reserved (maintaining memory map) */
tITCR itcr; /*interrupt test control */
tITEST itest; /*interrupt test status */
UINT8 rsv4[5]; /*reserved (maintaining memory map) */
tMEMSIZ0 memsiz0; /* */
tMEMSIZ1 memsiz1; /* */
tIRQCR irqcr; /*interrupt control register */
tHPRIO hprio; /*highest priority I interrupt */
UINT8 rsv5[8];/*reserved (maintaining memory map) */
tBKPCT0 bkpct0; /*breakpoint control register 0 */
tBKPCT1 bkpct1; /*breakpoint control register 1 */
tBKP0X bkp0x; /* */
tBKP0 bkp0; /*breakpoint address registers */
tBKP1X bkp1x; /* */
tBKP1 bkp1; /*breakpoint data registers */
volatile tPPAGE ppage; /*program page index register */
UINT8 rsv6; /*reserved (maintaining memory map) */
volatile tPORTK portk; /*port K data register */
volatile tDDRK ddrk; /*port K data direction register */
}tREGISTER;
/************************* Extern Variables **********************************/
/************************* #Defines ******************************************/
#define PTA0 0x01 /*bit masks */
#define PTA1 0x02
#define PTA2 0x04
#define PTA3 0x08
#define PTA4 0x10
#define PTA5 0x20
#define PTA6 0x40
#define PTA7 0x80
#define PTB0 0x01 /*bit masks */
#define PTB1 0x02
#define PTB2 0x04
#define PTB3 0x08
#define PTB4 0x10
#define PTB5 0x20
#define PTB6 0x40
#define PTB7 0x80
#define DDRA0 0x01 /*bit masks */
#define DDRA1 0x02
#define DDRA2 0x04
#define DDRA3 0x08
#define DDRA4 0x10
#define DDRA5 0x20
#define DDRA6 0x40
#define DDRA7 0x80
#define DDRB0 0x01 /*bit masks */
#define DDRB1 0x02
#define DDRB2 0x04
#define DDRB3 0x08
#define DDRB4 0x10
#define DDRB5 0x20
#define DDRB6 0x40
#define DDRB7 0x80
#define PTE0 0x01 /*bit masks */
#define PTE1 0x02
#define PTE2 0x04
#define PTE3 0x08
#define PTE4 0x10
#define PTE5 0x20
#define PTE6 0x40
#define PTE7 0x80
#define DDRE2 0x04 /*bit masks */
#define DDRE3 0x08
#define DDRE4 0x10
#define DDRE5 0x20
#define DDRE6 0x40
#define DDRE7 0x80
#define RDWE 0x04 /*bit masks */
#define LSTRE 0x08
#define NECLK 0x10
#define PIPOE 0x20
#define NOACCE 0x80
#define EME 0x01 /*bit masks */
#define EMK 0x02
#define IVIS 0x08
#define MODA 0x20
#define MODB 0x40
#define MODC 0x80
#define PUPAE 0x01 /*bit mask */
#define PUPBE 0x02
#define PUPEE 0x10
#define PUPKE 0x40
#define RDPA 0x01 /*bit mask */
#define RDPB 0x02
#define RDPE 0x10
#define RDPK 0x80
#define ESTR 0x01 /*bit mask */
#define RAMHAL 0x01 /*bit masks */
#define RAM11 0x08
#define RAM12 0x10
#define RAM13 0x20
#define RAM14 0x40
#define RAM15 0x80
#define REG11 0x08 /*bit masks */
#define REG12 0x10
#define REG13 0x20
#define REG14 0x40
#define REG15 0x80
#define EEON 0x01 /*bit masks */
#define EE12 0x10
#define EE13 0x20
#define EE14 0x40
#define EE15 0x80
#define ROMON 0x01 /*bit masks */
#define ROMHM 0x02
#define EXSTR0 0x04
#define EXSTR1 0x08
#define ADR0 0x01 /*bit masks */
#define ADR1 0x02
#define ADR2 0x04
#define ADR3 0x08
#define WRINT 0x10
#define INT0 0x01 /*bit masks */
#define INT2 0x02
#define INT3 0x04
#define INT6 0x08
//#define INT8 0x10
#define INTA 0x20
#define INTC 0x40
#define INTE 0x80
#define RAM_SW0 0x01 /*bit masks */
#define RAM_SW1 0x02
#define RAM_SW2 0x04
#define EEP_SW0 0x10
#define EEP_SW1 0x20
#define REG_SW0 0x80
#define PAG_SW0 0x01 /*bit masks */
#define PAG_SW1 0x02
#define ROM_SW0 0x40
#define ROM_SW1 0x80
#define IRQEN 0x40 /*bit masks */
#define IRQE 0x80
#define PSEL1 0x02 /*bit masks */
#define PSEL2 0x04
#define PSEL3 0x08
#define PSEL4 0x10
#define PSEL5 0x20
#define PSEL6 0x40
#define PSEL7 0x80
#define BKTAG 0x10
#define BKBDM 0x20
#define BKFULL 0x40
#define BKEN 0x80
#define BK1RW 0x01 /*bit masks */
#define BK1RWE 0x02
#define BK0RW 0x04
#define BK0RWE 0x08
#define BK1MBL 0x10
#define BK1MBH 0x20
#define BK0Mbl 0x40
#define BK0MBH 0x80
#define BK0V0 0x01 /*bit masks */
#define BK0V1 0x02
#define BK0V2 0x04
#define BK0V3 0x08
#define BK0V4 0x10
#define BK0V5 0x20
#define BK1V0 0x01 /*bit masks */
#define BK1V1 0x02
#define BK1V2 0x04
#define BK1V3 0x08
#define BK1V4 0x10
#define BK1V5 0x20
/************************* Macros ********************************************/
/************************* Prototypes ****************************************/
#endif /* End of Header file !defined */?? 快捷鍵說明
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