// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1C6Q240C6 Package PQFP240
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "FIFO_Buffer")
  (DATE "01/06/2009 02:54:42")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 8.0 Build 215 05/29/2008 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ns)

  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE clk\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1.13:1.13:1.13) (1.13:1.13:1.13))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE rst\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1.13:1.13:1.13) (1.13:1.13:1.13))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE write_to_stack\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1.135:1.135:1.135) (1.135:1.135:1.135))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ptr_gap\[0\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.421:0.421:0.421) (0.421:0.421:0.421))
        (IOPATH dataa regin (0.568:0.568:0.568) (0.568:0.568:0.568))
        (IOPATH dataa cout0 (0.434:0.434:0.434) (0.434:0.434:0.434))
        (IOPATH dataa cout1 (0.443:0.443:0.443) (0.443:0.443:0.443))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ptr_gap\[0\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1.291:1.291:1.291) (1.291:1.291:1.291))
        (PORT clk (1.147:1.147:1.147) (1.147:1.147:1.147))
        (PORT ena (1.664:1.664:1.664) (1.664:1.664:1.664))
        (IOPATH (posedge clk) regout (0.173:0.173:0.173) (0.173:0.173:0.173))
        (IOPATH (posedge aclr) regout (0.218:0.218:0.218) (0.218:0.218:0.218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (0.029:0.029:0.029))
      (SETUP ena (posedge clk) (0.029:0.029:0.029))
      (HOLD datain (posedge clk) (0.012:0.012:0.012))
      (HOLD ena (posedge clk) (0.012:0.012:0.012))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ptr_gap\[1\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.418:0.418:0.418) (0.418:0.418:0.418))
        (PORT datab (1.198:1.198:1.198) (1.198:1.198:1.198))
        (IOPATH dataa regin (0.568:0.568:0.568) (0.568:0.568:0.568))
        (IOPATH datab regin (0.467:0.467:0.467) (0.467:0.467:0.467))
        (IOPATH cin0 regin (0.603:0.603:0.603) (0.603:0.603:0.603))
        (IOPATH cin1 regin (0.606:0.606:0.606) (0.606:0.606:0.606))
        (IOPATH dataa cout0 (0.434:0.434:0.434) (0.434:0.434:0.434))
        (IOPATH datab cout0 (0.326:0.326:0.326) (0.326:0.326:0.326))
        (IOPATH cin0 cout0 (0.06:0.06:0.06) (0.06:0.06:0.06))
        (IOPATH dataa cout1 (0.443:0.443:0.443) (0.443:0.443:0.443))
        (IOPATH datab cout1 (0.333:0.333:0.333) (0.333:0.333:0.333))
        (IOPATH cin1 cout1 (0.062:0.062:0.062) (0.062:0.062:0.062))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ptr_gap\[1\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1.291:1.291:1.291) (1.291:1.291:1.291))
        (PORT clk (1.147:1.147:1.147) (1.147:1.147:1.147))
        (PORT ena (1.664:1.664:1.664) (1.664:1.664:1.664))
        (IOPATH (posedge clk) regout (0.173:0.173:0.173) (0.173:0.173:0.173))
        (IOPATH (posedge aclr) regout (0.218:0.218:0.218) (0.218:0.218:0.218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (0.029:0.029:0.029))
      (SETUP ena (posedge clk) (0.029:0.029:0.029))
      (HOLD datain (posedge clk) (0.012:0.012:0.012))
      (HOLD ena (posedge clk) (0.012:0.012:0.012))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ptr_gap\[2\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1.039:1.039:1.039) (1.039:1.039:1.039))
        (PORT datab (0.412:0.412:0.412) (0.412:0.412:0.412))
        (IOPATH dataa regin (0.568:0.568:0.568) (0.568:0.568:0.568))
        (IOPATH datab regin (0.467:0.467:0.467) (0.467:0.467:0.467))
        (IOPATH cin0 regin (0.603:0.603:0.603) (0.603:0.603:0.603))
        (IOPATH cin1 regin (0.606:0.606:0.606) (0.606:0.606:0.606))
        (IOPATH dataa cout0 (0.434:0.434:0.434) (0.434:0.434:0.434))
        (IOPATH datab cout0 (0.326:0.326:0.326) (0.326:0.326:0.326))
        (IOPATH cin0 cout0 (0.06:0.06:0.06) (0.06:0.06:0.06))
        (IOPATH dataa cout1 (0.443:0.443:0.443) (0.443:0.443:0.443))
        (IOPATH datab cout1 (0.333:0.333:0.333) (0.333:0.333:0.333))
        (IOPATH cin1 cout1 (0.062:0.062:0.062) (0.062:0.062:0.062))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ptr_gap\[2\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1.291:1.291:1.291) (1.291:1.291:1.291))
        (PORT clk (1.147:1.147:1.147) (1.147:1.147:1.147))
        (PORT ena (1.664:1.664:1.664) (1.664:1.664:1.664))
        (IOPATH (posedge clk) regout (0.173:0.173:0.173) (0.173:0.173:0.173))
        (IOPATH (posedge aclr) regout (0.218:0.218:0.218) (0.218:0.218:0.218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (0.029:0.029:0.029))
      (SETUP ena (posedge clk) (0.029:0.029:0.029))
      (HOLD datain (posedge clk) (0.012:0.012:0.012))
      (HOLD ena (posedge clk) (0.012:0.012:0.012))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ptr_gap\[3\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1.041:1.041:1.041) (1.041:1.041:1.041))
        (PORT datab (0.403:0.403:0.403) (0.403:0.403:0.403))
        (IOPATH dataa regin (0.568:0.568:0.568) (0.568:0.568:0.568))
        (IOPATH datab regin (0.467:0.467:0.467) (0.467:0.467:0.467))
        (IOPATH cin0 regin (0.603:0.603:0.603) (0.603:0.603:0.603))
        (IOPATH cin1 regin (0.606:0.606:0.606) (0.606:0.606:0.606))
        (IOPATH dataa cout (0.553:0.553:0.553) (0.553:0.553:0.553))
        (IOPATH datab cout (0.449:0.449:0.449) (0.449:0.449:0.449))
        (IOPATH cin0 cout (0.137:0.137:0.137) (0.137:0.137:0.137))
        (IOPATH cin1 cout (0.121:0.121:0.121) (0.121:0.121:0.121))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ptr_gap\[3\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1.291:1.291:1.291) (1.291:1.291:1.291))
        (PORT clk (1.147:1.147:1.147) (1.147:1.147:1.147))
        (PORT ena (1.664:1.664:1.664) (1.664:1.664:1.664))
        (IOPATH (posedge clk) regout (0.173:0.173:0.173) (0.173:0.173:0.173))
        (IOPATH (posedge aclr) regout (0.218:0.218:0.218) (0.218:0.218:0.218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (0.029:0.029:0.029))
      (SETUP ena (posedge clk) (0.029:0.029:0.029))
      (HOLD datain (posedge clk) (0.012:0.012:0.012))
      (HOLD ena (posedge clk) (0.012:0.012:0.012))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ptr_gap\[4\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1.043:1.043:1.043) (1.043:1.043:1.043))
        (PORT datab (0.412:0.412:0.412) (0.412:0.412:0.412))
        (IOPATH dataa regin (0.568:0.568:0.568) (0.568:0.568:0.568))
        (IOPATH datab regin (0.467:0.467:0.467) (0.467:0.467:0.467))
        (IOPATH cin regin (0.646:0.646:0.646) (0.646:0.646:0.646))
        (IOPATH dataa cout0 (0.434:0.434:0.434) (0.434:0.434:0.434))
        (IOPATH datab cout0 (0.326:0.326:0.326) (0.326:0.326:0.326))
        (IOPATH dataa cout1 (0.443:0.443:0.443) (0.443:0.443:0.443))
        (IOPATH datab cout1 (0.333:0.333:0.333) (0.333:0.333:0.333))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ptr_gap\[4\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1.291:1.291:1.291) (1.291:1.291:1.291))
        (PORT clk (1.147:1.147:1.147) (1.147:1.147:1.147))
        (PORT ena (1.664:1.664:1.664) (1.664:1.664:1.664))
        (IOPATH (posedge clk) regout (0.173:0.173:0.173) (0.173:0.173:0.173))
        (IOPATH (posedge aclr) regout (0.218:0.218:0.218) (0.218:0.218:0.218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (0.029:0.029:0.029))
      (SETUP ena (posedge clk) (0.029:0.029:0.029))
      (HOLD datain (posedge clk) (0.012:0.012:0.012))
      (HOLD ena (posedge clk) (0.012:0.012:0.012))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ptr_gap\[5\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1.042:1.042:1.042) (1.042:1.042:1.042))
        (PORT datad (0.43:0.43:0.43) (0.43:0.43:0.43))
        (IOPATH dataa regin (0.568:0.568:0.568) (0.568:0.568:0.568))
        (IOPATH datad regin (0.238:0.238:0.238) (0.238:0.238:0.238))
        (IOPATH cin regin (0.646:0.646:0.646) (0.646:0.646:0.646))
        (IOPATH cin0 regin (0.603:0.603:0.603) (0.603:0.603:0.603))
        (IOPATH cin1 regin (0.606:0.606:0.606) (0.606:0.606:0.606))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ptr_gap\[5\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1.291:1.291:1.291) (1.291:1.291:1.291))
        (PORT clk (1.147:1.147:1.147) (1.147:1.147:1.147))
        (PORT ena (1.664:1.664:1.664) (1.664:1.664:1.664))
        (IOPATH (posedge clk) regout (0.173:0.173:0.173) (0.173:0.173:0.173))
        (IOPATH (posedge aclr) regout (0.218:0.218:0.218) (0.218:0.218:0.218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (0.029:0.029:0.029))
      (SETUP ena (posedge clk) (0.029:0.029:0.029))
      (HOLD datain (posedge clk) (0.012:0.012:0.012))
      (HOLD ena (posedge clk) (0.012:0.012:0.012))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE Equal0\~111.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (0.416:0.416:0.416) (0.416:0.416:0.416))
        (PORT datac (0.353:0.353:0.353) (0.353:0.353:0.353))
        (PORT datad (0.432:0.432:0.432) (0.432:0.432:0.432))
        (IOPATH datab combout (0.34:0.34:0.34) (0.34:0.34:0.34))
        (IOPATH datac combout (0.225:0.225:0.225) (0.225:0.225:0.225))
        (IOPATH datad combout (0.088:0.088:0.088) (0.088:0.088:0.088))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE read_from_stack\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1.135:1.135:1.135) (1.135:1.135:1.135))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ptr_gap\[0\]\~404.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4.579:4.579:4.579) (4.579:4.579:4.579))
        (PORT datab (0.994:0.994:0.994) (0.994:0.994:0.994))
        (PORT datac (1.01:1.01:1.01) (1.01:1.01:1.01))
        (PORT datad (4.586:4.586:4.586) (4.586:4.586:4.586))
        (IOPATH dataa combout (0.454:0.454:0.454) (0.454:0.454:0.454))
        (IOPATH datab combout (0.34:0.34:0.34) (0.34:0.34:0.34))
        (IOPATH datac combout (0.225:0.225:0.225) (0.225:0.225:0.225))
        (IOPATH datad combout (0.088:0.088:0.088) (0.088:0.088:0.088))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE Equal0\~110.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.424:0.424:0.424) (0.424:0.424:0.424))
        (PORT datab (0.403:0.403:0.403) (0.403:0.403:0.403))
        (PORT datac (0.431:0.431:0.431) (0.431:0.431:0.431))
        (PORT datad (0.425:0.425:0.425) (0.425:0.425:0.425))
        (IOPATH dataa combout (0.454:0.454:0.454) (0.454:0.454:0.454))
        (IOPATH datab combout (0.34:0.34:0.34) (0.34:0.34:0.34))
        (IOPATH datac combout (0.225:0.225:0.225) (0.225:0.225:0.225))
        (IOPATH datad combout (0.088:0.088:0.088) (0.088:0.088:0.088))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE Equal2\~67.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (0.419:0.419:0.419) (0.419:0.419:0.419))