--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    12:44:09 03/02/09
-- Design Name:    
-- Module Name:    microoven - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity microoven is
    Port ( key0 : in std_logic;
           key1 : in std_logic;
           key2 : in std_logic;
           key3 : in std_logic;
           key4 : in std_logic;
           key5 : in std_logic;
           key6 : in std_logic;
           key7 : in std_logic;
           key8 : in std_logic;
           key9 : in std_logic;
           Clear : in std_logic;
           Start : in std_logic;
           Set : in std_logic;
           Door : in std_logic;
           Clk : in std_logic;
           H_LED : out std_logic;
           M_LED : out std_logic;
           L_LED : out std_logic;
           a : out std_logic;
           b : out std_logic;
           c : out std_logic;
           d : out std_logic;
           e : out std_logic;
           f : out std_logic;
           g : out std_logic);
end microoven;

architecture Behavioral of microoven is
component PICunit
    Port (	PIC_clk : in std_logic;
	 			Key_num : in std_logic_vector(2 downto 0);
         	Set : in std_logic;
          	Clear : in std_logic;
			  	Door: in std_logic;
				Start : in std_logic;
--				TC : in std_logic;
				COUNT : in std_logic_vector(3 downto 0);
				Counter_EN : out std_logic;
				Counter_Reset : out std_logic;
			  	LED : out std_logic_vector(2 downto 0)
				);
end component;
component key_number_encoder
    Port ( clk : in std_logic;
	 		  key_en	: in std_logic;
	        key_in : in std_logic_vector(9 downto 0);
	        kload  : out std_logic;
           Qn : out std_logic_vector(3 downto 0));
end component;
component counter
    Port ( CLK : in std_logic;
           RESET : in std_logic;
           CE : in std_logic;
           LOAD : in std_logic;
           DIR : in std_logic;
           DIN : in std_logic_vector(3 downto 0);
--			  TC : out std_logic;
           COUNT : inout std_logic_vector(3 downto 0));
end component;
component clkdiv2
    Port (
		clkin : in std_logic;
		clkoutsec : out std_logic);
end component;
component clkdiv3
    Port (
		clkin : in std_logic;
		clkoutmsec : out std_logic);
end component;
component seven_segnment
    Port (
		HEX : in std_logic_vector(3 downto 0);
		output : out std_logic_vector(6 downto 0)
	  );
end component;

--wire
signal tempkey :std_logic_vector (9 downto 0);
signal tempkeynum :std_logic_vector (2 downto 0);
signal tempLED :std_logic_vector (2 downto 0);
signal temp_Counter_EN,temp_Counter_Reset :std_logic;
signal temp_kload :std_logic;
--signal temp_TC :std_logic;
signal temp_Qn :std_logic_vector(3 downto 0);
signal temp_COUNT :std_logic_vector(3 downto 0);
signal temp_clkoutmsec,temp_clkoutsec :std_logic;
signal temp_seventseg :std_logic_vector(6 downto 0);

begin
	tempkey(0)<=key0; 
	tempkey(1)<=key1; 
	tempkey(2)<=key2; 
	tempkey(3)<=key3; 
	tempkey(4)<=key4; 
	tempkey(5)<=key5; 
	tempkey(6)<=key6; 
	tempkey(7)<=key7; 
	tempkey(8)<=key8; 
	tempkey(9)<=key9;
	tempkeynum(0) <=key7; 
	tempkeynum(1) <=key8; 	
	tempkeynum(2) <=key9;
	u1 : PICunit port map (temp_clkoutmsec,tempkeynum,Set,
									Clear,Door,Start,temp_COUNT,temp_Counter_EN,
									temp_Counter_Reset,tempLED);
--										u1 : PICunit port map (temp_clkoutmsec,tempkeynum,temp_Key_EN,Set,
--									Clear,Door,temp_TC,Start,temp_Counter_EN,
--									temp_Counter_Reset,tempLED);
	u2 : key_number_encoder port map(temp_clkoutsec,Set,tempkey,
											temp_kload,temp_Qn);
--	u2 : key_number_encoder port map(temp_clkoutsec,temp_Key_EN,tempkey,
--											temp_kload,temp_Qn);
	u3 : counter port map(temp_clkoutsec,temp_Counter_Reset,temp_Counter_EN,
          					temp_kload,'0',temp_Qn,temp_COUNT);
--	u3 : counter port map(temp_clkoutsec,temp_Counter_Reset,temp_Counter_EN,
--          						temp_kload,'0',temp_Qn,temp_TC,temp_COUNT);
	u4 : clkdiv2 port map (Clk,temp_clkoutsec);
	u6 : clkdiv3 port map (Clk,temp_clkoutmsec);
	u5 : seven_segnment port map (temp_COUNT,temp_seventseg);
	g<= temp_seventseg(6);
	f<= temp_seventseg(5);
	e<= temp_seventseg(4);
	d<= temp_seventseg(3);
	c<= temp_seventseg(2);
	b<= temp_seventseg(1);
	a<= temp_seventseg(0);

	H_LED<= tempLED(2);
   M_LED<= tempLED(1);
   L_LED<= tempLED(0);


end Behavioral;