?? pxa-regs.h
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#define MCSR_FIFOE (1 << 4) /* FIFO error */#define GSR __REG(0x4050001C) /* Global Status Register */#define GSR_CDONE (1 << 19) /* Command Done */#define GSR_SDONE (1 << 18) /* Status Done */#define GSR_RDCS (1 << 15) /* Read Completion Status */#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */#define GSR_SCR (1 << 9) /* Secondary Codec Ready */#define GSR_PCR (1 << 8) /* Primary Codec Ready */#define GSR_MINT (1 << 7) /* Mic In Interrupt */#define GSR_POINT (1 << 6) /* PCM Out Interrupt */#define GSR_PIINT (1 << 5) /* PCM In Interrupt */#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */#define GSR_MIINT (1 << 1) /* Modem In Interrupt */#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */#define CAR __REG(0x40500020) /* CODEC Access Register */#define CAR_CAIP (1 << 0) /* Codec Access In Progress */#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */#define MOCR __REG(0x40500100) /* Modem Out Control Register */#define MOCR_FEIE (1 << 3) /* FIFO Error */#define MICR __REG(0x40500108) /* Modem In Control Register */#define MICR_FEIE (1 << 3) /* FIFO Error */#define MOSR __REG(0x40500110) /* Modem Out Status Register */#define MOSR_FIFOE (1 << 4) /* FIFO error */#define MISR __REG(0x40500118) /* Modem In Status Register */#define MISR_FIFOE (1 << 4) /* FIFO error */#define MODR __REG(0x40500140) /* Modem FIFO Data Register */#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec *//* * USB Device Controller */#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */#define UDCCR __REG(0x40600000) /* UDC Control Register */#define UDCCR_UDE (1 << 0) /* UDC enable */#define UDCCR_UDA (1 << 1) /* UDC active */#define UDCCR_RSM (1 << 2) /* Device resume */#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */#define UDCCR_REM (1 << 7) /* Reset interrupt mask */#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */#define UDCCS0_OPR (1 << 0) /* OUT packet ready */#define UDCCS0_IPR (1 << 1) /* IN packet ready */#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */#define UDCCS0_SST (1 << 4) /* Sent stall */#define UDCCS0_FST (1 << 5) /* Force stall */#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */#define UDCCS0_SA (1 << 7) /* Setup active *//* Bulk IN - Endpoint 1,6,11 */#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */#define UDCCS_BI_SST (1 << 4) /* Sent stall */#define UDCCS_BI_FST (1 << 5) /* Force stall */#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet *//* Bulk OUT - Endpoint 2,7,12 */#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */#define UDCCS_BO_DME (1 << 3) /* DMA enable */#define UDCCS_BO_SST (1 << 4) /* Sent stall */#define UDCCS_BO_FST (1 << 5) /* Force stall */#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */#define UDCCS_BO_RSP (1 << 7) /* Receive short packet *//* Isochronous IN - Endpoint 3,8,13 */#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */#define UDCCS_II_TSP (1 << 7) /* Transmit short packet *//* Isochronous OUT - Endpoint 4,9,14 */#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */#define UDCCS_IO_DME (1 << 3) /* DMA enable */#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */#define UDCCS_IO_RSP (1 << 7) /* Receive short packet *//* Interrupt IN - Endpoint 5,10,15 */#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */#define UDCCS_INT_SST (1 << 4) /* Sent stall */#define UDCCS_INT_FST (1 << 5) /* Force stall */#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */#if defined(CONFIG_PXA27X)/* * USB Host Controller */#define UHCREV __REG(0x4C000000)#define UHCHCON __REG(0x4C000004)#define UHCCOMS __REG(0x4C000008)#define UHCINTS __REG(0x4C00000C)#define UHCINTE __REG(0x4C000010)#define UHCINTD __REG(0x4C000014)#define UHCHCCA __REG(0x4C000018)#define UHCPCED __REG(0x4C00001C)#define UHCCHED __REG(0x4C000020)#define UHCCCED __REG(0x4C000024)#define UHCBHED __REG(0x4C000028)#define UHCBCED __REG(0x4C00002C)#define UHCDHEAD __REG(0x4C000030)#define UHCFMI __REG(0x4C000034)#define UHCFMR __REG(0x4C000038)#define UHCFMN __REG(0x4C00003C)#define UHCPERS __REG(0x4C000040)#define UHCLST __REG(0x4C000044)#define UHCRHDA __REG(0x4C000048)#define UHCRHDB __REG(0x4C00004C)#define UHCRHS __REG(0x4C000050)#define UHCRHPS1 __REG(0x4C000054)#define UHCRHPS2 __REG(0x4C000058)#define UHCRHPS3 __REG(0x4C00005C)#define UHCSTAT __REG(0x4C000060)#define UHCHR __REG(0x4C000064)#define UHCHIE __REG(0x4C000068)#define UHCHIT __REG(0x4C00006C)#define UHCHR_FSBIR (1<<0)#define UHCHR_FHR (1<<1)#define UHCHR_CGR (1<<2)#define UHCHR_SSDC (1<<3)#define UHCHR_UIT (1<<4)#define UHCHR_SSE (1<<5)#define UHCHR_PSPL (1<<6)#define UHCHR_PCPL (1<<7)#define UHCHR_SSEP0 (1<<9)#define UHCHR_SSEP1 (1<<10)#define UHCHR_SSEP2 (1<<11)#define UHCHIE_UPRIE (1<<13)#define UHCHIE_UPS2IE (1<<12)#define UHCHIE_UPS1IE (1<<11)#define UHCHIE_TAIE (1<<10)#define UHCHIE_HBAIE (1<<8)#define UHCHIE_RWIE (1<<7)#endif/* * Fast Infrared Communication Port */#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */?? 快捷鍵說明
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