/* * (C) Copyright 2001 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * * * TODO: clean-up *//* * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM? * * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum * parameters from the datasheet are: * Tclk = 7.5ns (CL = 2) * Trp = 15ns * Trc = 60ns * Trcd = 15ns * Trfc = 66ns * * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock * period is 10ns and the parameters needed for the Timing Register are: * CASL = CL = 2 clock cycles * PTA = Trp = 15ns / 10ns = 2 clock cycles * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles * LDF = 2 clock cycles (but can be extended to meet board-level timing) * RFTA = Trfc = 66ns / 10ns= 7 clock cycles * RCD = Trcd = 15ns / 10ns= 2 clock cycles * * The actual bit settings in the register would be: * * CASL = 0b01 * PTA = 0b01 * CTP = 0b10 * LDF = 0b01 * RFTA = 0b011 * RCD = 0b01 * * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay * defined as Trc rather than Trfc. * When using DIMM modules, most but not all of the required timing parameters can be read * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc * are not available from the EEPROM */#include <common.h>#include "mip405.h"#include <asm/processor.h>#include <405gp_i2c.h>#include <miiphy.h>#include "../common/common_util.h"#include <i2c.h>#include <rtc.h>extern block_dev_desc_t * scsi_get_dev(int dev);extern block_dev_desc_t * ide_get_dev(int dev);#undef SDRAM_DEBUG#define ENABLE_ECC /* for ecc boards */#define FALSE           0#define TRUE            1/* stdlib.h causes some compatibility problems; should fixe these! -- wd */#ifndef __ldiv_t_definedtypedef struct {	long int quot;		/* Quotient	*/	long int rem;		/* Remainder	*/} ldiv_t;extern ldiv_t ldiv (long int __numer, long int __denom);# define __ldiv_t_defined	1#endif#define PLD_PART_REG 		PER_PLD_ADDR + 0#define PLD_VERS_REG 		PER_PLD_ADDR + 1#define PLD_BOARD_CFG_REG 	PER_PLD_ADDR + 2#define PLD_IRQ_REG 		PER_PLD_ADDR + 3#define PLD_COM_MODE_REG 	PER_PLD_ADDR + 4#define PLD_EXT_CONF_REG 	PER_PLD_ADDR + 5#define MEGA_BYTE (1024*1024)typedef struct {	unsigned char boardtype; /* Board revision and Population Options */	unsigned char cal;		/* cas Latency (will be programmend as cal-1) */	unsigned char trp;		/* datain27 in clocks */	unsigned char trcd;		/* datain29 in clocks */	unsigned char tras;		/* datain30 in clocks */	unsigned char tctp;		/* tras - trcd in clocks */	unsigned char am;		/* Address Mod (will be programmed as am-1) */	unsigned char sz;		/* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */	unsigned char ecc;		/* if true, ecc is enabled */} sdram_t;#if defined(CONFIG_MIP405T)const sdram_t sdram_table[] = {	{ 0x0F,	/* MIP405T Rev A, 64MByte -1 Board */		3,	/* Case Latenty = 3 */		3,	/* trp 20ns / 7.5 ns datain[27] */		3,	/* trcd 20ns /7.5 ns (datain[29]) */		6,	/* tras 44ns /7.5 ns  (datain[30]) */		4,	/* tcpt 44 - 20ns = 24ns */		2,	/* Address Mode = 2 (12x9x4) */		3,	/* size value (32MByte) */		0},	/* ECC disabled */	{ 0xff, /* terminator */	  0xff,	  0xff,	  0xff,	  0xff,	  0xff,	  0xff,	  0xff }};#elseconst sdram_t sdram_table[] = {	{ 0x0f,	/* Rev A, 128MByte -1 Board */		3,	/* Case Latenty = 3 */		3,	/* trp 20ns / 7.5 ns datain[27] */		3,	/* trcd 20ns /7.5 ns (datain[29]) */		6,	/* tras 44ns /7.5 ns  (datain[30]) */		4,	/* tcpt 44 - 20ns = 24ns */		3,	/* Address Mode = 3 */		5,	/* size value */		1},	/* ECC enabled */	{ 0x07,	/* Rev A, 64MByte -2 Board */		3,	/* Case Latenty = 3 */		3,	/* trp 20ns / 7.5 ns datain[27] */		3,	/* trcd 20ns /7.5 ns (datain[29]) */		6,	/* tras 44ns /7.5 ns  (datain[30]) */		4,	/* tcpt 44 - 20ns = 24ns */		2,	/* Address Mode = 2 */		4,	/* size value */		1},	/* ECC enabled */	{ 0x03,	/* Rev A, 128MByte -4 Board */		3,	/* Case Latenty = 3 */		3,	/* trp 20ns / 7.5 ns datain[27] */		3,	/* trcd 20ns /7.5 ns (datain[29]) */		6,	/* tras 44ns /7.5 ns  (datain[30]) */		4,	/* tcpt 44 - 20ns = 24ns */		3,	/* Address Mode = 3 */		5,	/* size value */		1},	/* ECC enabled */	{ 0x1f,	/* Rev B, 128MByte -3 Board */		3,	/* Case Latenty = 3 */		3,	/* trp 20ns / 7.5 ns datain[27] */		3,	/* trcd 20ns /7.5 ns (datain[29]) */		6,	/* tras 44ns /7.5 ns  (datain[30]) */		4,	/* tcpt 44 - 20ns = 24ns */		3,	/* Address Mode = 3 */		5,	/* size value */		1},	/* ECC enabled */	{ 0x2f,	/* Rev C, 128MByte -3 Board */		3,	/* Case Latenty = 3 */		3,	/* trp 20ns / 7.5 ns datain[27] */		3,	/* trcd 20ns /7.5 ns (datain[29]) */		6,	/* tras 44ns /7.5 ns  (datain[30]) */		4,	/* tcpt 44 - 20ns = 24ns */		3,	/* Address Mode = 3 */		5,	/* size value */		1},	/* ECC enabled */	{ 0xff, /* terminator */	  0xff,	  0xff,	  0xff,	  0xff,	  0xff,	  0xff,	  0xff }};#endif /*CONFIG_MIP405T */void SDRAM_err (const char *s){#ifndef SDRAM_DEBUG	DECLARE_GLOBAL_DATA_PTR;	(void) get_clocks ();	gd->baudrate = 9600;	serial_init ();#endif	serial_puts ("\n");	serial_puts (s);	serial_puts ("\n enable SDRAM_DEBUG for more info\n");	for (;;);}unsigned char get_board_revcfg (void){	out8 (PER_BOARD_ADDR, 0);	return (in8 (PER_BOARD_ADDR));}#ifdef SDRAM_DEBUGvoid write_hex (unsigned char i){	char cc;	cc = i >> 4;	cc &= 0xf;	if (cc > 9)		serial_putc (cc + 55);	else		serial_putc (cc + 48);	cc = i & 0xf;	if (cc > 9)		serial_putc (cc + 55);	else		serial_putc (cc + 48);}void write_4hex (unsigned long val){	write_hex ((unsigned char) (val >> 24));	write_hex ((unsigned char) (val >> 16));	write_hex ((unsigned char) (val >> 8));	write_hex ((unsigned char) val);}#endifint init_sdram (void){	DECLARE_GLOBAL_DATA_PTR;	unsigned long	tmp, baseaddr;	unsigned short	i;	unsigned char	trp_clocks,			trcd_clocks,			tras_clocks,			trc_clocks,			tctp_clocks;	unsigned char	cal_val;	unsigned char	bc;	unsigned long	sdram_tim, sdram_bank;	/*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/	(void) get_clocks ();	gd->baudrate = 9600;	serial_init ();	/* set up the pld */	mtdcr (ebccfga, pb7ap);	mtdcr (ebccfgd, PLD_AP);	mtdcr (ebccfga, pb7cr);	mtdcr (ebccfgd, PLD_CR);	/* THIS IS OBSOLETE */	/* set up the board rev reg*/	mtdcr (ebccfga, pb5ap);	mtdcr (ebccfgd, BOARD_AP);	mtdcr (ebccfga, pb5cr);	mtdcr (ebccfgd, BOARD_CR);#ifdef SDRAM_DEBUG	/* get all informations from PLD */	serial_puts ("\nPLD Part  0x");	bc = in8 (PLD_PART_REG);	write_hex (bc);	serial_puts ("\nPLD Vers  0x");	bc = in8 (PLD_VERS_REG);	write_hex (bc);	serial_puts ("\nBoard Rev 0x");	bc = in8 (PLD_BOARD_CFG_REG);	write_hex (bc);	serial_puts ("\n");#endif	/* check board */	bc = in8 (PLD_PART_REG);#if defined(CONFIG_MIP405T)	if((bc & 0x80)==0)		SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");#else	if((bc & 0x80)==0x80)		SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");#endif	/* set-up the chipselect machine */	mtdcr (ebccfga, pb0cr);		/* get cs0 config reg */	tmp = mfdcr (ebccfgd);	if ((tmp & 0x00002000) == 0) {		/* MPS Boot, set up the flash */		mtdcr (ebccfga, pb1ap);		mtdcr (ebccfgd, FLASH_AP);		mtdcr (ebccfga, pb1cr);		mtdcr (ebccfgd, FLASH_CR);	} else {		/* Flash boot, set up the MPS */		mtdcr (ebccfga, pb1ap);		mtdcr (ebccfgd, MPS_AP);		mtdcr (ebccfga, pb1cr);		mtdcr (ebccfgd, MPS_CR);	}	/* set up UART0 (CS2) and UART1 (CS3) */	mtdcr (ebccfga, pb2ap);	mtdcr (ebccfgd, UART0_AP);	mtdcr (ebccfga, pb2cr);	mtdcr (ebccfgd, UART0_CR);	mtdcr (ebccfga, pb3ap);	mtdcr (ebccfgd, UART1_AP);	mtdcr (ebccfga, pb3cr);	mtdcr (ebccfgd, UART1_CR);	bc = in8 (PLD_BOARD_CFG_REG);#ifdef SDRAM_DEBUG	serial_puts ("\nstart SDRAM Setup\n");	serial_puts ("\nBoard Rev: ");	write_hex (bc);	serial_puts ("\n");#endif	i = 0;	baseaddr = CFG_SDRAM_BASE;	while (sdram_table[i].sz != 0xff) {		if (sdram_table[i].boardtype == bc)			break;		i++;	}	if (sdram_table[i].boardtype != bc)		SDRAM_err ("No SDRAM table found for this board!!!\n");#ifdef SDRAM_DEBUG	serial_puts (" found table ");	write_hex (i);	serial_puts (" \n");#endif	/* since the ECC initialisation needs some time,	 * we show that we're alive	 */	if (sdram_table[i].ecc)		serial_puts ("\nInitializing SDRAM, Please stand by");	cal_val = sdram_table[i].cal - 1;	/* Cas Latency */	trp_clocks = sdram_table[i].trp;	/* 20ns / 7.5 ns datain[27] */	trcd_clocks = sdram_table[i].trcd;	/* 20ns /7.5 ns (datain[29]) */	tras_clocks = sdram_table[i].tras;	/* 44ns /7.5 ns  (datain[30]) */	/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */	tctp_clocks = sdram_table[i].tctp;	/* 44 - 20ns = 24ns */	/* trc_clocks is sum of trp_clocks + tras_clocks */	trc_clocks = trp_clocks + tras_clocks;	/* get SDRAM timing register */	mtdcr (memcfga, mem_sdtr1);	sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;	/* insert CASL value */	sdram_tim |= ((unsigned long) (cal_val)) << 23;	/* insert PTA value */	sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;	/* insert CTP value */	sdram_tim |=			((unsigned long) (trc_clocks - trp_clocks -							  trcd_clocks)) << 16;	/* insert LDF (always 01) */	sdram_tim |= ((unsigned long) 0x01) << 14;	/* insert RFTA value */	sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;	/* insert RCD value */	sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;	tmp = ((unsigned long) (sdram_table[i].am - 1) << 13);	/* AM = 3 */	/* insert SZ value; */	tmp |= ((unsigned long) sdram_table[i].sz << 17);	/* get SDRAM bank 0 register */	mtdcr (memcfga, mem_mb0cf);	sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;	sdram_bank |= (baseaddr | tmp | 0x01);#ifdef SDRAM_DEBUG	serial_puts ("sdtr: ");	write_4hex (sdram_tim);	serial_puts ("\n");#endif	/* write SDRAM timing register */	mtdcr (memcfga, mem_sdtr1);	mtdcr (memcfgd, sdram_tim);#ifdef SDRAM_DEBUG	serial_puts ("mb0cf: ");	write_4hex (sdram_bank);	serial_puts ("\n");#endif	/* write SDRAM bank 0 register */	mtdcr (memcfga, mem_mb0cf);	mtdcr (memcfgd, sdram_bank);	if (get_bus_freq (tmp) > 110000000) {	/* > 110MHz */		/* get SDRAM refresh interval register */		mtdcr (memcfga, mem_rtr);		tmp = mfdcr (memcfgd) & ~0x3FF80000;		tmp |= 0x07F00000;	} else {		/* get SDRAM refresh interval register */		mtdcr (memcfga, mem_rtr);		tmp = mfdcr (memcfgd) & ~0x3FF80000;		tmp |= 0x05F00000;	}	/* write SDRAM refresh interval register */	mtdcr (memcfga, mem_rtr);