library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PL_CPSK2 is
port(clk:in std_logic;
   start:in std_logic;
       x:in std_logic;
       y:out std_logic);
end entity PL_CPSK2;
architecture behav of PL_CPSK2 is
signal q:integer range 0 to 3;
begin
process(clk)
begin
if clk'event and clk='1' then
    if start='0' then q<=0;
    elsif q=0 then q<=q+1;
        if x='1' then y<='1';
        else y<='0';
        end if;
    elsif q=3 then q<=0;
   else  q<=q+1;
   end if;
end if;
end process;
end architecture behav;