?? cpsk.rpt
字號:
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\pingdai\dpsk\cpsk.rpt
cpsk
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC19 dout
| +----------------------------- LC21 dout1
| | +--------------------------- LC18 dout2
| | | +------------------------- LC17 dout3
| | | | +----------------------- LC32 |PL_CPSK:1|q1
| | | | | +--------------------- LC31 |PL_CPSK:1|q0
| | | | | | +------------------- LC30 |PL_CPSK:1|f1
| | | | | | | +----------------- LC20 |PL_CPSK:1|f2
| | | | | | | | +--------------- LC29 |PL_CPSK2:2|q1
| | | | | | | | | +------------- LC28 |PL_CPSK2:2|q0
| | | | | | | | | | +----------- LC27 |PL_DPSK2:12|q1
| | | | | | | | | | | +--------- LC26 |PL_DPSK2:12|q0
| | | | | | | | | | | | +------- LC25 |PL_DPSK2:12|xx
| | | | | | | | | | | | | +----- LC24 |PL_DPSK:11|q1
| | | | | | | | | | | | | | +--- LC23 |PL_DPSK:11|q0
| | | | | | | | | | | | | | | +- LC22 |PL_DPSK:11|xx
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC19 -> * - - - - - - - - - - - - - - - | - * | <-- dout
LC21 -> - * - * - - - - - - - - - - - - | - * | <-- dout1
LC18 -> - * * - - - - - - - - - - - - - | - * | <-- dout2
LC17 -> * - - * - - - - - - - - * - - - | - * | <-- dout3
LC32 -> - - - - * - * * - - - - - - - - | - * | <-- |PL_CPSK:1|q1
LC31 -> - * - - * * - - - - - - - - - - | - * | <-- |PL_CPSK:1|q0
LC30 -> - * - - - - * - - - - - - - - - | - * | <-- |PL_CPSK:1|f1
LC20 -> - * - - - - - * - - - - - - - - | - * | <-- |PL_CPSK:1|f2
LC29 -> - - - * - - - - * - - - - - - - | - * | <-- |PL_CPSK2:2|q1
LC28 -> - - - * - - - - * * - - - - - - | - * | <-- |PL_CPSK2:2|q0
LC27 -> * - - - - - - - - - * - * - - - | - * | <-- |PL_DPSK2:12|q1
LC26 -> * - - - - - - - - - * * * - - - | - * | <-- |PL_DPSK2:12|q0
LC25 -> * - - - - - - - - - - - * - - - | - * | <-- |PL_DPSK2:12|xx
LC24 -> - - * - - - - - - - - - - * - * | - * | <-- |PL_DPSK:11|q1
LC23 -> - - * - - - - - - - - - - * * * | - * | <-- |PL_DPSK:11|q0
LC22 -> - - * - - - - - - - - - - - - * | - * | <-- |PL_DPSK:11|xx
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
4 -> - - * - - - - - - - - - - - - * | - * | <-- din
5 -> * - * * * * * * * * * * * * * * | - * | <-- start
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\pingdai\dpsk\cpsk.rpt
cpsk
** EQUATIONS **
clk : INPUT;
din : INPUT;
start : INPUT;
-- Node name is 'dout' = '|PL_DPSK2:12|:4'
-- Equation name is 'dout', type is output
dout = TFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !dout & !dout3 & _LC025 & _LC026 & _LC027 & start
# dout & dout3 & _LC025 & _LC026 & _LC027 & start
# dout & !dout3 & !_LC025 & _LC026 & _LC027 & start
# !dout & dout3 & !_LC025 & _LC026 & _LC027 & start;
-- Node name is 'dout1' = '|PL_CPSK:1|:6'
-- Equation name is 'dout1', type is output
dout1 = DFFE( _EQ002 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = dout2 & _LC030 & _LC031
# !dout2 & _LC020 & _LC031
# dout1 & !_LC031;
-- Node name is 'dout2' = '|PL_DPSK:11|:4'
-- Equation name is 'dout2', type is output
dout2 = TFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = din & dout2 & _LC022 & !_LC023 & !_LC024 & start
# !din & !dout2 & _LC022 & !_LC023 & !_LC024 & start
# din & !dout2 & !_LC022 & !_LC023 & !_LC024 & start
# !din & dout2 & !_LC022 & !_LC023 & !_LC024 & start;
-- Node name is 'dout3' = '|PL_CPSK2:2|:4'
-- Equation name is 'dout3', type is output
dout3 = _LC017~NOT;
_LC017~NOT = TFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = dout1 & dout3 & !_LC028 & !_LC029 & start
# !dout1 & !dout3 & !_LC028 & !_LC029 & start;
-- Node name is '|PL_CPSK:1|:10' = '|PL_CPSK:1|f1'
-- Equation name is '_LC030', type is buried
_LC030 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC032 & start
# _LC030 & !start;
-- Node name is '|PL_CPSK:1|:11' = '|PL_CPSK:1|f2'
-- Equation name is '_LC020', type is buried
_LC020 = DFFE( _EQ006 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC032 & start
# !_LC020 & !start;
-- Node name is '|PL_CPSK:1|:9' = '|PL_CPSK:1|q0'
-- Equation name is '_LC031', type is buried
_LC031 = DFFE( _EQ007 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC031 & start;
-- Node name is '|PL_CPSK:1|:8' = '|PL_CPSK:1|q1'
-- Equation name is '_LC032', type is buried
_LC032 = DFFE( _EQ008 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC031 & _LC032 & start
# !_LC031 & !_LC032 & start;
-- Node name is '|PL_CPSK2:2|:7' = '|PL_CPSK2:2|q0'
-- Equation name is '_LC028', type is buried
_LC028 = DFFE( _EQ009 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC028 & start;
-- Node name is '|PL_CPSK2:2|:6' = '|PL_CPSK2:2|q1'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( _EQ010 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !_LC028 & _LC029 & start
# _LC028 & !_LC029 & start;
-- Node name is '|PL_DPSK2:12|:7' = '|PL_DPSK2:12|q0'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( _EQ011 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC026 & start;
-- Node name is '|PL_DPSK2:12|:6' = '|PL_DPSK2:12|q1'
-- Equation name is '_LC027', type is buried
_LC027 = DFFE( _EQ012 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC026 & _LC027 & start
# !_LC026 & !_LC027 & start;
-- Node name is '|PL_DPSK2:12|:8' = '|PL_DPSK2:12|xx'
-- Equation name is '_LC025', type is buried
_LC025 = TFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !dout3 & _LC025 & _LC026 & _LC027 & start
# dout3 & !_LC025 & _LC026 & _LC027 & start;
-- Node name is '|PL_DPSK:11|:7' = '|PL_DPSK:11|q0'
-- Equation name is '_LC023', type is buried
_LC023 = DFFE( _EQ014 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = _LC023 & start;
-- Node name is '|PL_DPSK:11|:6' = '|PL_DPSK:11|q1'
-- Equation name is '_LC024', type is buried
_LC024 = DFFE( _EQ015 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = _LC023 & _LC024 & start
# !_LC023 & !_LC024 & start;
-- Node name is '|PL_DPSK:11|:8' = '|PL_DPSK:11|xx'
-- Equation name is '_LC022', type is buried
_LC022 = TFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = din & !_LC022 & !_LC023 & !_LC024 & start
# din & _LC022 & !_LC023 & !_LC024
# _LC022 & !start;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information g:\pingdai\dpsk\cpsk.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,828K
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