Project Information                                g:\pingdai\dpsk\pl_dpsk.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/04/2006 20:51:48

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


PL_DPSK


** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

pl_dpsk   EP1K10TC100-1    3      1      0    0         0  %    6        1  %

User Pins:                 3      1      0  



Project Information                                g:\pingdai\dpsk\pl_dpsk.rpt

** PROJECT TIMING MESSAGES **

Warning: Timing characteristics of device EP1K10TC100-1 are preliminary


Project Information                                g:\pingdai\dpsk\pl_dpsk.rpt

** FILE HIERARCHY **



|lpm_add_sub:78|
|lpm_add_sub:78|addcore:adder|
|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                       g:\pingdai\dpsk\pl_dpsk.rpt
pl_dpsk

***** Logic for device 'pl_dpsk' compiled without errors.




Device: EP1K10TC100-1

ACEX 1K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF
    Enable Lock Output                         = OFF

                                                                   
                                                                   
                  R R R R   R R           R R R R   R R R R R R    
                  E E E E   E E           E E E E   E E E E E E    
                  S S S S   S S V         S S S S   S S S S S S ^  
                  E E E E   E E C         E E E E V E E E E E E D  
                # R R R R   R R C         R R R R C R R R R R R A  
                T V V V V G V V I G G G G V V V V C V V V V V V T  
                C E E E E N E E N N N N N E E E E I E E E E E E A  
                K D D D D D D D T D D D D D D D D O D D D D D D 0  
              ----------------------------------------------------_ 
             / 100  98  96  94  92  90  88  86  84  82  80  78  76   |_ 
            /     99  97  95  93  91  89  87  85  83  81  79  77    | 
^CONF_DONE |  1                                                    75 | ^DCLK 
     ^nCEO |  2                                                    74 | ^nCE 
      #TDO |  3                                                    73 | #TDI 
     VCCIO |  4                                                    72 | VCCINT 
  RESERVED |  5                                                    71 | RESERVED 
  RESERVED |  6                                                    70 | RESERVED 
  RESERVED |  7                                                    69 | RESERVED 
  RESERVED |  8                                                    68 | RESERVED 
  RESERVED |  9                                                    67 | VCCIO 
  RESERVED | 10                                                    66 | GND 
       GND | 11                                                    65 | RESERVED 
    VCCINT | 12                                                    64 | RESERVED 
  RESERVED | 13                   EP1K10TC100-1                    63 | RESERVED 
         y | 14                                                    62 | RESERVED 
  RESERVED | 15                                                    61 | RESERVED 
  RESERVED | 16                                                    60 | VCCINT 
     VCCIO | 17                                                    59 | GND 
       GND | 18                                                    58 | RESERVED 
  RESERVED | 19                                                    57 | RESERVED 
  RESERVED | 20                                                    56 | RESERVED 
  RESERVED | 21                                                    55 | RESERVED 
  RESERVED | 22                                                    54 | ^MSEL0 
  RESERVED | 23                                                    53 | ^MSEL1 
      #TMS | 24                                                    52 | VCCINT 
  ^nSTATUS | 25                                                    51 | ^nCONFIG 
           |      27  29  31  33  35  37  39  41  43  45  47  49  _| 
            \   26  28  30  32  34  36  38  40  42  44  46  48  50   | 
             \----------------------------------------------------- 
                R R R R R R R R R V G V x c s G G R V R R R R R R  
                E E E E E E E E E C N C   l t N N E C E E E E E E  
                S S S S S S S S S C D C   k a D D S C S S S S S S  
                E E E E E E E E E I   _     r _   E I E E E E E E  
                R R R R R R R R R N   C     t C   R O R R R R R R  
                V V V V V V V V V T   K       K   V   V V V V V V  
                E E E E E E E E E     L       L   E   E E E E E E  
                D D D D D D D D D     K       K   D   D D D D D D  
                                                                   
                                                                   


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant. 


Device-Specific Information:                       g:\pingdai\dpsk\pl_dpsk.rpt
pl_dpsk

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
B15      6/ 8( 75%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       2/22(  9%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 3/6      ( 50%)
Total I/O pins used:                             1/60     (  1%)
Total logic cells used:                          6/576    (  1%)
Total embedded cells used:                       0/48     (  0%)
Total EABs used:                                 0/3      (  0%)
Average fan-in:                                 3.16/4    ( 79%)
Total fan-in:                                  19/2304    (  0%)

Total input pins required:                       3
Total input I/O cell registers required:         0
Total output pins required:                      1
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                      6
Total flipflops required:                        4
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                         0/ 576   (  0%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  EA  13  14  15  16  17  18  19  20  21  22  23  24  Total(LC/EC)
 A:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 B:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   6   0   0   0   0   0   0   0   0   0      6/0  
 C:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  

Total:   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   6   0   0   0   0   0   0   0   0   0      6/0  



Device-Specific Information:                       g:\pingdai\dpsk\pl_dpsk.rpt
pl_dpsk

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  39      -     -    -    --      INPUT  G          ^    0    0    0    0  clk
  40      -     -    -    --      INPUT             ^    0    0    0    4  start
  38      -     -    -    --      INPUT             ^    0    0    0    1  x


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                       g:\pingdai\dpsk\pl_dpsk.rpt
pl_dpsk

** OUTPUTS **