library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PL_CPSK is
port(clk:in std_logic;
   start:in std_logic;
       x:in std_logic;
       p1,p2,y:out std_logic);
end entity PL_CPSK;
architecture behav of PL_CPSK is
signal q:std_logic_vector(1 downto 0);
signal f1,f2:std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then
    if start='0' then q<="00";
elsif q<="01" then f1 <='1';f2<='0';q<=q+1;
elsif q="11" then f1<='0';f2<='1';q<="00";
else  f1<='0';f2<='1';q<=q+1;
    end if;
end if;
end process;
process(clk,x)
begin
if clk'event and clk='1' then
     if q(0)='1' then
         if x='1' then y<=f1;
         else y<=f2;
      end if;
    end if;
end if;
end process;
p1<=f1;p2<=f2;
end architecture behav;