LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
  PORT (clk :IN STD_LOGIC;
K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
RESET:IN STD_LOGIC;
        EN:in STD_LOGIC;
        Q: out STD_LOGIC_VECTOR(9 DOWNTO 0));
END ENTITY dds;
ARCHITECTURE ART OF DDS IS
  COMPONENT SUM99 IS
PORT(clk :IN STD_LOGIC;
K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
RESET:IN STD_LOGIC;
        EN:in STD_LOGIC;
        OUT1: out STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT SUM99;
COMPONENT REG1 IS
PORT(clk :IN STD_LOGIC;
     D:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
     Q: out STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT REG1;
COMPONENT ROM IS
PORT(clk :IN STD_LOGIC;
     ADDER:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
     OUTP: out STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT ROM;
COMPONENT REG2 IS
PORT(clk :IN STD_LOGIC;
     D:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
     Q: out STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT REG2;
SIGNAL S1 : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL S2 : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL S3 : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
U0:SUM99 PORT MAP(K=>K,EN=>EN,RESET=>RESET,CLK=>CLK,OUT1=>S1);
U1:REG1 PORT MAP(D=>S1,CLK=>CLK,Q=>S2);
U2:ROM PORT MAP(ADDER=>S2,CLK=>CLK,OUTP=>S3);
U3:REG2 PORT MAP(D=>S3,CLK=>CLK,Q=>Q);
END ARCHITECTURE ART;