(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 6 22 13 10 50)
   (author "Xilinx, Inc.")
   (program "ChipScope Pro Core Generator" (version "9.1.03i (build 09103.7.81.1059)"))))
   (comment "********************************************************************")
   (comment "Component name:                 vio")
   (comment "Device family:                  Virtex5")
   (comment "SRL16 Type:                     SRLC16/E")
   (comment "Asynchronous Input Port Width:  2")
   (comment "Asynchronous Output Port Width: 64")
   (comment "Clock Edge Used for Sampling:   rising edge")
   (comment "Force RPM Grid Usage: no")
   (comment "********************************************************************")
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2006 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_use_inv_clk = 0 ")
       (comment "c_core_type = 9 ")
       (comment "c_use_sync_out = 0 ")
       (comment "c_mfg_id = 1 ")
       (comment "c_async_out_width = 64 ")
       (comment "c_srl16_type = 2 ")
       (comment "c_device_family = 14 ")
       (comment "InstanceName = vio ")
       (comment "c_minor_version = 1 ")
       (comment "c_major_version = 9 ")
       (comment "c_async_in_width = 2 ")
       (comment "c_use_async_in = 1 ")
       (comment "c_use_sync_in = 0 ")
       (comment "c_build_revision = 2 ")
       (comment "c_use_async_out = 1 ")
       (comment "c_sync_out_width = 1 ")
       (comment "c_sync_in_width = 1 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDCE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLR (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDR (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port R (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDRE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port R (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell INV (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell LUT1 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell LUT3 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell LUT6 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port O (direction OUTPUT))
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port I4 (direction INPUT))
                   (port I5 (direction INPUT))
               )
           )
       )
       (cell MUXCY_L (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port LO (direction OUTPUT))
               )
           )
       )
       (cell MUXF7 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell XORCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port LI (direction INPUT))
                   (port CI (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell vio
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename async_in_1_ "async_in<1>") (direction INPUT))
   (port ( rename async_in_0_ "async_in<0>") (direction INPUT))
   (port ( rename async_out_63_ "async_out<63>") (direction OUTPUT))
   (port ( rename async_out_62_ "async_out<62>") (direction OUTPUT))
   (port ( rename async_out_61_ "async_out<61>") (direction OUTPUT))
   (port ( rename async_out_60_ "async_out<60>") (direction OUTPUT))
   (port ( rename async_out_59_ "async_out<59>") (direction OUTPUT))
   (port ( rename async_out_58_ "async_out<58>") (direction OUTPUT))
   (port ( rename async_out_57_ "async_out<57>") (direction OUTPUT))
   (port ( rename async_out_56_ "async_out<56>") (direction OUTPUT))
   (port ( rename async_out_55_ "async_out<55>") (direction OUTPUT))