?? byte_counter.v
字號:
module byte_count_module(CLK, RESET, START, BYTE_COUNTER);// Ports declarationinput CLK;input RESET;input START;output [15:0] BYTE_COUNTER;reg [15:0] BYTE_COUNTER;reg [15:0] counter;always @(posedge CLK or posedge RESET)begin if (RESET == 1) begin counter = 16'h0000; end // the ack is delayed which starts the counter else if (START == 1) begin counter = counter + 8; endendalways @(posedge CLK)begin BYTE_COUNTER = counter;endendmodule // End of Module
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