/////////////////////////////////////////////////////////////////////////////////		Name of module //              23/1/06 - So far Mentor Precision indicates the current system runs as 101 MHz.///////////////////////////////////////////////////////////////////////////////module TRANSMIT_TOP(TX_DATA, TX_DATA_VALID, TX_CLK, RESET, TX_START, TX_ACK, TX_UNDERRUN, TX_IFG_DELAY,RXTXLINKFAULT, LOCALLINKFAULT,TX_STATS_VALID,TXSTATREGPLUS,TXD, TXC, FC_TRANS_PAUSEDATA, FC_TRANS_PAUSEVAL, FC_TX_PAUSEDATA,FC_TX_PAUSEVALID,TX_CFG_REG_VALUE,TX_CFG_REG_VALID);/////////////////////////////////////////////////////////////////////////////////		Input and output ports definitions/////////////////////////////////////////////////////////////////////////////////Input from user logicinput [63:0] TX_DATA;input [7:0] TX_DATA_VALID; // To accept the data valid to be availableinput TX_CLK;input RESET;input TX_START; // This signify the first frame of datainput TX_UNDERRUN; // this will cause an error to be injected into the datainput [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal//input to transmit fault signalsinput RXTXLINKFAULT;input LOCALLINKFAULT;input [31:0] TX_CFG_REG_VALUE;input TX_CFG_REG_VALID;//output to stat registeroutput TX_STATS_VALID;output [24:0] TXSTATREGPLUS; // a pulse for each reg for stats//output to user logicoutput TX_ACK; //Generated by a counter//output to XGMIIoutput [63:0] TXD;output [7:0] TXC;//output [15:0] BYTE_COUNTER_OUT;//Pause inputs//Transmit pause framesinput [15:0] FC_TRANS_PAUSEDATA; //pause frame datainput FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent//apply pause timinginput [15:0] FC_TX_PAUSEDATA;input FC_TX_PAUSEVALID;/////////////////////////////////////////////////////////////////////////////////		Definitions and parameters/////////////////////////////////////////////////////////////////////////////////possibility to put this in a package.//opcode definitionsparameter PAUSE_OPCODE = 16'b1000100000001000; //8808parameter  VLAN_OPCODE = 16'b1000000100000000; //8100//frame size definitionsparameter VLAN_FRAME_SIZE = 16'b0000010111110010;//1522 bytesparameter JUMBO_FRAME_SIZE = 16'b0010001100101000;//9000 bytesparameter NORMAL_FRAME_SIZE = 16'b0000010111101110;//1518 bytesparameter MIN_FRAME_SIZE = 16'b0000000000111100; //60 bytes//Frame definitionparameter IDLE_FRAME = 8'b00000111; //only six preambles as the first preamble is converted into a start flagparameter IDLE_FRAME_8BYTES = 64'b0000011100000111000001110000011100000111000001110000011100000111;parameter START_SEQ = 64'b1010101110101010101010101010101010101010101010101010101011111011;parameter LOCAL_FAULT_SEQ = 64'b0000000100000000000000000000000000000001000000000000000000000000;parameter REMOTE_FAULT_SEQ = 64'b0000001000000000000000000000000000000010000000000000000000000000;parameter START_FRAME = 8'b11111011; //only valid in frame 0parameter TERMINATE_FRAME = 8'b11111101;parameter SFD_FRAME = 8'b10101011;parameter PREAMBLE_FRAME = 8'b10101010;parameter ERROR_FRAME = 8'b11111110;parameter SOURCE_ADDR = 48'h010101010101;parameter DEST_ADDR = 48'h101010101010;parameter PAUSE_FRAME_LENGTH = 8'h02;//need a parameter for min frame gap.//Link fault signalling// send lane 0/////////////////////////////////////////////////////////////////////////////////		Registers and wires///////////////////////////////////////////////////////////////////////////////wire  TX_ACK;reg  [24:0] TXSTATREGPLUS;reg  TX_STATS_VALID;reg FRAME_START;wire reset_int;reg [15:0] DELAY_ACK;reg [7:0] TX_DATA_VALID_REG;reg [7:0] TX_DATA_VALID_DEL1;reg [7:0] TX_DATA_VALID_DEL2;reg [7:0] TX_DATA_VALID_DEL3;reg [7:0] TX_DATA_VALID_DEL4;reg [7:0] TX_DATA_VALID_DEL5;reg [7:0] TX_DATA_VALID_DEL6;reg [7:0] TX_DATA_VALID_DEL7;reg [7:0] TX_DATA_VALID_DEL8;reg [7:0] TX_DATA_VALID_DEL9;reg [7:0] TX_DATA_VALID_DEL10;reg [7:0] TX_DATA_VALID_DEL11;reg [7:0] TX_DATA_VALID_DEL12;reg [7:0] TX_DATA_VALID_DEL13;reg [7:0] TX_DATA_VALID_DEL14;reg [7:0] TX_DATA_VALID_DEL15;reg [63:0] TX_DATA_DEL1;reg [63:0] TX_DATA_DEL2;reg [63:0] TX_DATA_DEL3;reg [63:0] TX_DATA_DEL4;reg [63:0] TX_DATA_DEL5;reg [63:0] TX_DATA_DEL6;reg [63:0] TX_DATA_DEL7;reg [63:0] TX_DATA_DEL8;reg [63:0] TX_DATA_DEL9;reg [63:0] TX_DATA_DEL10;reg [63:0] TX_DATA_DEL11;reg [63:0] TX_DATA_DEL12;reg [63:0] TX_DATA_DEL13;reg [63:0] TX_DATA_DEL14;reg [63:0] TX_DATA_DEL15;reg [7:0] OVERFLOW_VALID;reg [63:0] OVERFLOW_DATA;reg [63:0] TXD;reg [7:0] TXC;reg [63:0] TX_DATA_REG, TX_DATA_VALID_DELAY;wire [31:0] CRC_32_64;wire [15:0] BYTE_COUNTER;reg frame_start_del;reg transmit_pause_frame_del, transmit_pause_frame_del2, transmit_pause_frame, append_start_pause, append_start_pause_del , transmit_pause_frame_valid, reset_err_pause, load_CRC8, transmit_pause_frame_del3;reg [7:0] tx_data_int;reg start_CRC8, START_CRC8_DEL;reg append_end_frame;reg insert_error;reg [7:0] store_tx_data_valid;reg [63:0] store_tx_data;reg [31:0] store_CRC64;reg [7:0] store_valid;reg load_final_CRC;reg [15:0] final_byte_count, byte_count_reg;wire [31:0] CRC_OUT;reg [9:0] append_reg;reg [15:0] length_register;reg tx_undderrun_int;reg [15:0] MAX_FRAME_SIZE;reg vlan_enabled_int;reg jumbo_enabled_int;reg tx_enabled_int;reg fcs_enabled_int;reg reset_tx_int;reg read_ifg_int;reg apply_pause_delay;reg [15:0] store_pause_frame;reg [63:0] TXD_PAUSE_DEL0;reg [63:0] TXD_PAUSE_DEL1;reg [63:0] TXD_PAUSE_DEL2;reg [7:0] TXC_PAUSE_DEL0;reg [7:0] TXC_PAUSE_DEL1;reg [7:0] TXC_PAUSE_DEL2;reg PAUSEVAL_DEL;reg PAUSEVAL_DEL1;reg PAUSEVAL_DEL2;wire RESET_ERR_PAUSE;reg set_pause_stats;reg [15:0] store_transmit_pause_value;reg [3:0] pause_frame_counter;reg [63:0] shift_pause_data;reg [7:0] shift_pause_valid;reg [7:0] shift_pause_valid_del;reg [14:0] byte_count_stat;reg [24:0] txstatplus_int;/////////////////////////////////////////////////////////////////////////////////		Start of code/////////////////////////////////////////////////////////////////////////////////TODO//RX side. need to be able to receive data and calculate the CRC switching between 64 and 8 bit datapath.//Therefore, the data need to be counted correctly.//ERROR checking module or process will be needed. This will check if frame is correct length.//Need to be able to remove redundant frames or columns and also padding. The error module will//also check the tx_underrun signal as well.//need to be able to cut-off bytes. //Need to add the link fault signalling and config registers.//TX side. need to be able to insert the CRC with the data.//need to define the first column of txd which is START 6 PRE and SFD.//need to be able invert data_valid for txc.//need to be able to transmit IDLEs.//Format of output//IDLE 07, START FB TERMINATE FD SFD 10101011 PREAMBLE 10101010  ERROR FE.//IDLE START PREAMBLE SFD DA SA L/T DATA TERMINATE IDLE/////////////////////////////////////////////////////////////////////////////////		Ack counter/////////////////////////////////////////////////////////////////////////////////Ack counter. need to be able to load the frame length, pause frame inter frame delay into the ack counter// as this will delay the ack signal. The ack signal will initiate the rest of the data transmission from the// user logic.//need to stop the ack signal from transmitting when a PAUSE frame is transmitting// Connect DUT to test bench ack_counter U_ACK_CNT(.clock(TX_CLK),.reset(reset_int | reset_tx_int),	.ready(FRAME_START | transmit_pause_frame),.tx_start(TX_START),.max_count(DELAY_ACK),.tx_ack(TX_ACK));//CRC for 64 bit data//This seem to be one of the culprit for the timing violationCRC32_D64 U_CRC64(.DATA_IN(TX_DATA_REG), //need to swap between pause data.CLK(TX_CLK),	.RESET(reset_int | TX_ACK | append_start_pause),.START(frame_start_del | transmit_pause_frame_valid),.CRC_OUT(CRC_32_64) //need to switch to output some how for a pause frame);//CRC for 8 bit dataCRC32_D8 U_CRC8(.DATA_IN(tx_data_int), //8bit data.CLK(TX_CLK),.RESET(reset_int),.START(start_CRC8),  //this signal will be use to start.LOAD(load_CRC8), //use this to load first.CRC_IN(CRC_32_64),.CRC_OUT(CRC_OUT));//The start signal need to be high for the count//This seem to be one of the culprit for the timing violationbyte_count_module U_byte_count_module(.CLK(TX_CLK),.RESET(reset_int | TX_ACK),.START(frame_start_del & FRAME_START),.BYTE_COUNTER(BYTE_COUNTER));/////////////////////////////////////////////////////////////////////////////////	PAUSE FRAME///////////////////////////////////////////////////////////////////////////////always @(posedge TX_CLK)begin  PAUSEVAL_DEL <= FC_TRANS_PAUSEVAL;  PAUSEVAL_DEL1 <= PAUSEVAL_DEL;  PAUSEVAL_DEL2 <= PAUSEVAL_DEL1;endalways @(posedge TX_CLK or posedge reset_int)begin  if (reset_int) begin    transmit_pause_frame <= 0;  end  else if (PAUSEVAL_DEL2) begin    transmit_pause_frame <= 1;  end   else if (pause_frame_counter == 8) begin    transmit_pause_frame <= 0;  end endalways @(posedge TX_CLK or posedge reset_int)begin  if (reset_int) begin    set_pause_stats <= 0;  end  else if (PAUSEVAL_DEL2) begin    set_pause_stats <= 1;  end  else if (append_end_frame) begin    set_pause_stats <= 0;  endendalways @(posedge TX_CLK or posedge reset_int)begin  if (reset_int) begin    TXD_PAUSE_DEL0 <= 0;    TXD_PAUSE_DEL1 <= 0;    TXD_PAUSE_DEL2 <= 0;        TXC_PAUSE_DEL0 <= 0;    TXC_PAUSE_DEL1 <= 0;    TXC_PAUSE_DEL2 <= 0;        store_transmit_pause_value <= 0;  end  else if (FC_TRANS_PAUSEVAL) begin    store_transmit_pause_value <= FC_TRANS_PAUSEDATA;    TXD_PAUSE_DEL1 <= {DEST_ADDR, SOURCE_ADDR[47:32]};    TXD_PAUSE_DEL2 <= {SOURCE_ADDR[31:0], PAUSE_FRAME_LENGTH, PAUSE_OPCODE, FC_TRANS_PAUSEDATA};    TXC_PAUSE_DEL1 <= 8'hff;    TXC_PAUSE_DEL2 <= 8'hff;      end endalways @(posedge TX_CLK or posedge reset_int)begin  if (reset_int) begin    pause_frame_counter <= 0;  end  else if (transmit_pause_frame & !FRAME_START) begin    pause_frame_counter <= pause_frame_counter + 1;  end endalways @(posedge TX_CLK or posedge reset_int)begin  if (reset_int) begin    shift_pause_data <= 0;    shift_pause_valid_del <= 0;    shift_pause_valid <= 0;  end  else if (transmit_pause_frame & !FRAME_START) begin    if (pause_frame_counter == 0) begin      shift_pause_data <= TXD_PAUSE_DEL1;    end    else if (pause_frame_counter == 1) begin      shift_pause_data <= TXD_PAUSE_DEL2;    end    else begin      shift_pause_data <= 0;    end         if (pause_frame_counter == 7) begin      shift_pause_valid <= 8'h0f;    end    else if (pause_frame_counter < 7) begin      shift_pause_valid <= 8'hff;    end    else begin      shift_pause_valid <= 0;    end     shift_pause_valid_del <= shift_pause_valid;  end  else begin    shift_pause_data <= 0;    shift_pause_valid <= 0;    shift_pause_valid_del <= shift_pause_valid;  end endalways @(posedge reset_int or posedge TX_CLK)begin  if (reset_int) begin    FRAME_START <= 0;  end  else if (TX_ACK) begin