?? transmittop.v
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end else if (append_end_frame) begin TX_DATA_VALID_DEL14 <= OVERFLOW_VALID; end TX_DATA_VALID_DEL15 <= TX_DATA_VALID_DEL14; TXC <= TX_DATA_VALID_DEL15; endendalways @(posedge TX_CLK or posedge reset_int)begin if (reset_int) begin TX_DATA_DEL1 <= 0; TX_DATA_DEL2 <= 0; TX_DATA_DEL3 <= 0; TX_DATA_DEL4 <= 0; TX_DATA_DEL5 <= 0; TX_DATA_DEL6 <= 0; TX_DATA_DEL7 <= 0; TX_DATA_DEL8 <= 0; TX_DATA_DEL9 <= 0; TX_DATA_DEL10 <= 0; TX_DATA_DEL11 <= 0; TX_DATA_DEL12 <= 0; TX_DATA_DEL13 <= 0; TX_DATA_DEL14 <= 0; TX_DATA_DEL15 <= 0; OVERFLOW_DATA <= IDLE_FRAME_8BYTES; end else begin TX_DATA_DEL1 <= TX_DATA_REG; TX_DATA_DEL2 <= TX_DATA_DEL1; TX_DATA_DEL3 <= TX_DATA_DEL2; TX_DATA_DEL4 <= TX_DATA_DEL3; TX_DATA_DEL5 <= TX_DATA_DEL4; TX_DATA_DEL6 <= TX_DATA_DEL5; TX_DATA_DEL7 <= TX_DATA_DEL6; TX_DATA_DEL8 <= TX_DATA_DEL7; TX_DATA_DEL9 <= TX_DATA_DEL8; TX_DATA_DEL10 <= TX_DATA_DEL9; TX_DATA_DEL11 <= TX_DATA_DEL10; TX_DATA_DEL12 <= TX_DATA_DEL11; TX_DATA_DEL13 <= TX_DATA_DEL12; TX_DATA_DEL14 <= TX_DATA_DEL13; if (load_final_CRC) begin case (TX_DATA_VALID_DEL13) 8'b00000000 : begin if (fcs_enabled_int) begin TX_DATA_DEL14[31:0] <= CRC_OUT[31:0]; if (insert_error) begin TX_DATA_DEL14[39:32] <= ERROR_FRAME; TX_DATA_DEL14[47:40] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14[39:32] <= TERMINATE_FRAME; TX_DATA_DEL14[47:40] <= IDLE_FRAME; end TX_DATA_DEL14[55:48] <= IDLE_FRAME; TX_DATA_DEL14[63:56] <= IDLE_FRAME; end else begin if (insert_error) begin TX_DATA_DEL14[7:0] <= ERROR_FRAME; TX_DATA_DEL14[15:8] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14[7:0] <= TERMINATE_FRAME; TX_DATA_DEL14[15:8] <= IDLE_FRAME; end TX_DATA_DEL14[23:16] <= IDLE_FRAME; TX_DATA_DEL14[31:24] <= IDLE_FRAME; TX_DATA_DEL14[39:32] <= IDLE_FRAME; TX_DATA_DEL14[47:40] <= IDLE_FRAME; TX_DATA_DEL14[55:48] <= IDLE_FRAME; TX_DATA_DEL14[63:56] <= IDLE_FRAME; end OVERFLOW_DATA <= IDLE_FRAME_8BYTES; end 8'b00000001 : begin if (fcs_enabled_int) begin TX_DATA_DEL14[7:0] <= TX_DATA_DEL13[7:0]; TX_DATA_DEL14[39:8] <= CRC_OUT[31:0]; if (insert_error) begin TX_DATA_DEL14[47:40] <= ERROR_FRAME; TX_DATA_DEL14[55:48] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14[47:40] <= TERMINATE_FRAME; TX_DATA_DEL14[55:48] <= IDLE_FRAME; end TX_DATA_DEL14[63:56] <= IDLE_FRAME; TX_DATA_DEL14 <= TX_DATA_DEL13; end else begin TX_DATA_DEL14[7:0] <= TX_DATA_DEL13[7:0]; if (insert_error) begin TX_DATA_DEL14[15:8] <= ERROR_FRAME; TX_DATA_DEL14[23:16] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14[15:8] <= TERMINATE_FRAME; TX_DATA_DEL14[23:16] <= IDLE_FRAME; end TX_DATA_DEL14[31:24] <= IDLE_FRAME; TX_DATA_DEL14[39:32] <= IDLE_FRAME; TX_DATA_DEL14[47:40] <= IDLE_FRAME; TX_DATA_DEL14[55:48] <= IDLE_FRAME; TX_DATA_DEL14[63:56] <= IDLE_FRAME; TX_DATA_DEL14 <= TX_DATA_DEL13; end OVERFLOW_DATA <= IDLE_FRAME_8BYTES; end 8'b00000011 : begin if (fcs_enabled_int) begin TX_DATA_DEL14[15:0] <= TX_DATA_DEL13[15:0]; TX_DATA_DEL14[47:16] <= CRC_OUT[31:0]; if (insert_error) begin TX_DATA_DEL14[55:48] <= ERROR_FRAME; TX_DATA_DEL14[63:56] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14[55:48] <= TERMINATE_FRAME; TX_DATA_DEL14[63:56] <= IDLE_FRAME; end end else begin TX_DATA_DEL14[15:0] <= TX_DATA_DEL13[15:0]; if (insert_error) begin TX_DATA_DEL14[23:16] <= ERROR_FRAME; TX_DATA_DEL14[31:24] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14[23:16] <= TERMINATE_FRAME; TX_DATA_DEL14[31:24] <= IDLE_FRAME; end TX_DATA_DEL14[39:32] <= IDLE_FRAME; TX_DATA_DEL14[47:40] <= IDLE_FRAME; TX_DATA_DEL14[55:48] <= IDLE_FRAME; TX_DATA_DEL14[63:56] <= IDLE_FRAME; end OVERFLOW_DATA <= IDLE_FRAME_8BYTES; end 8'b00000111 : begin if (fcs_enabled_int) begin TX_DATA_DEL14[23:0] <= TX_DATA_DEL13[23:0]; TX_DATA_DEL14[55:24] <= CRC_OUT[31:0]; OVERFLOW_DATA <= IDLE_FRAME_8BYTES; if (insert_error) begin TX_DATA_DEL14[63:56] <= ERROR_FRAME; OVERFLOW_DATA[7:0] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14[63:56] <= TERMINATE_FRAME; end end else begin TX_DATA_DEL14[23:0] <= TX_DATA_DEL13[23:0]; TX_DATA_DEL14[55:24] <= CRC_OUT[31:0]; OVERFLOW_DATA <= IDLE_FRAME_8BYTES; if (insert_error) begin TX_DATA_DEL14[31:24] <= ERROR_FRAME; TX_DATA_DEL14[39:32] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14[39:32] <= IDLE_FRAME; end TX_DATA_DEL14[47:40] <= IDLE_FRAME; TX_DATA_DEL14[55:48] <= IDLE_FRAME; TX_DATA_DEL14[63:56] <= IDLE_FRAME; end end 8'b00001111 : begin if (fcs_enabled_int) begin TX_DATA_DEL14[31:0] <= TX_DATA_DEL13[31:0]; TX_DATA_DEL14[63:32]<= CRC_OUT[31:0]; if (insert_error) begin OVERFLOW_DATA [7:0] <= ERROR_FRAME; OVERFLOW_DATA[15:8] <= TERMINATE_FRAME; end else begin OVERFLOW_DATA [7:0]<= TERMINATE_FRAME; OVERFLOW_DATA [15:8]<= IDLE_FRAME; end OVERFLOW_DATA [23:16]<= IDLE_FRAME; OVERFLOW_DATA [31:24]<= IDLE_FRAME; OVERFLOW_DATA [39:32]<= IDLE_FRAME; OVERFLOW_DATA [47:40]<= IDLE_FRAME; OVERFLOW_DATA [55:48]<= IDLE_FRAME; OVERFLOW_DATA [63:56]<= IDLE_FRAME; end else begin TX_DATA_DEL14[31:0] <= TX_DATA_DEL13[31:0]; OVERFLOW_DATA <= IDLE_FRAME_8BYTES; if (insert_error) begin TX_DATA_DEL14 [39:32] <= ERROR_FRAME; TX_DATA_DEL14[47:40] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14 [39:32]<= TERMINATE_FRAME; TX_DATA_DEL14 [47:40]<= IDLE_FRAME; end TX_DATA_DEL14[55:48] <= IDLE_FRAME; TX_DATA_DEL14[63:56] <= IDLE_FRAME; end end 8'b00011111 : begin if (fcs_enabled_int) begin TX_DATA_DEL14[39:0] <= TX_DATA_DEL13[39:0]; TX_DATA_DEL14[63:40] <= CRC_OUT[23:0]; OVERFLOW_DATA [7:0]<= CRC_OUT[31:24]; if (insert_error) begin OVERFLOW_DATA [15:8]<= ERROR_FRAME; OVERFLOW_DATA [23:16]<= TERMINATE_FRAME; end else begin OVERFLOW_DATA [15:8]<= TERMINATE_FRAME; OVERFLOW_DATA [23:16]<= IDLE_FRAME; end OVERFLOW_DATA [31:24]<= IDLE_FRAME; OVERFLOW_DATA [39:32]<= IDLE_FRAME; OVERFLOW_DATA [47:40]<= IDLE_FRAME; OVERFLOW_DATA [55:48]<= IDLE_FRAME; OVERFLOW_DATA [63:56]<= IDLE_FRAME; end else begin TX_DATA_DEL14[39:0] <= TX_DATA_DEL13[39:0]; OVERFLOW_DATA <= IDLE_FRAME_8BYTES; if (insert_error) begin TX_DATA_DEL14 [47:40] <= ERROR_FRAME; TX_DATA_DEL14[55:48] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14 [47:40]<= TERMINATE_FRAME; TX_DATA_DEL14 [55:48]<= IDLE_FRAME; end TX_DATA_DEL14[63:56] <= IDLE_FRAME; end end 8'b00111111 : begin if (fcs_enabled_int) begin TX_DATA_DEL14[47:0] <= TX_DATA_DEL13[47:0]; TX_DATA_DEL14[63:48] <= CRC_OUT[15:0]; OVERFLOW_DATA [15:0]<= CRC_OUT[31:16]; if (insert_error) begin OVERFLOW_DATA [23:16]<= ERROR_FRAME; OVERFLOW_DATA [31:24]<= TERMINATE_FRAME; end else begin OVERFLOW_DATA [23:16]<= TERMINATE_FRAME; OVERFLOW_DATA [31:24]<= IDLE_FRAME; end OVERFLOW_DATA [39:32]<= IDLE_FRAME; OVERFLOW_DATA [47:40]<= IDLE_FRAME; OVERFLOW_DATA [55:48]<= IDLE_FRAME; OVERFLOW_DATA [63:56]<= IDLE_FRAME; end else begin TX_DATA_DEL14[47:0] <= TX_DATA_DEL13[47:0]; if (insert_error) begin TX_DATA_DEL14 [55:48] <= ERROR_FRAME; TX_DATA_DEL14[63:56] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14 [55:48]<= TERMINATE_FRAME; TX_DATA_DEL14 [63:56]<= IDLE_FRAME; end end end 8'b01111111 : begin if (fcs_enabled_int) begin TX_DATA_DEL14[55:0] <= TX_DATA_DEL13[55:0]; TX_DATA_DEL14[63:56] <= CRC_OUT[7:0]; OVERFLOW_DATA [23:0]<= CRC_OUT[31:8]; if (insert_error) begin OVERFLOW_DATA [31:24]<= ERROR_FRAME; OVERFLOW_DATA [39:32]<= TERMINATE_FRAME; end else begin OVERFLOW_DATA [31:24]<= TERMINATE_FRAME; OVERFLOW_DATA [39:32]<= IDLE_FRAME; end OVERFLOW_DATA [47:40]<= IDLE_FRAME; OVERFLOW_DATA [55:48]<= IDLE_FRAME; OVERFLOW_DATA [63:56]<= IDLE_FRAME; end else begin TX_DATA_DEL14[55:0] <= TX_DATA_DEL13[55:0]; OVERFLOW_DATA <= IDLE_FRAME_8BYTES; if (insert_error) begin TX_DATA_DEL14 [63:56] <= ERROR_FRAME; OVERFLOW_DATA[7:0] <= TERMINATE_FRAME; end else begin TX_DATA_DEL14 [63:56]<= TERMINATE_FRAME; OVERFLOW_DATA [7:0]<= IDLE_FRAME; end end end endcase end else if (append_end_frame) begin TX_DATA_DEL14 <= OVERFLOW_DATA; end TX_DATA_DEL15 <= TX_DATA_DEL14; TXD <= TX_DATA_DEL15; endendalways @(posedge TX_CLK or posedge reset_int)begin if (reset_int) begin store_tx_data_valid <= 0; store_tx_data <= 0; store_CRC64 <= 0; tx_data_int <= 0; end else if (load_CRC8) begin store_tx_data_valid <= TX_DATA_VALID_DEL2; store_tx_data <= TX_DATA_DEL2; store_CRC64 <= CRC_32_64; end else begin store_tx_data_valid[6:0] <= store_tx_data_valid[7:1]; tx_data_int <= store_tx_data[7:0]; store_tx_data[55:0] <= store_tx_data[63:8]; endend//Start CRC8 and load CRC8always @(posedge TX_CLK or posedge reset_int)begin if (reset_int) begin start_CRC8 <= 0; START_CRC8_DEL <= 0; end else begin start_CRC8 <= store_tx_data_valid[0]; START_CRC8_DEL <= start_CRC8; endendalways @(posedge TX_CLK or posedge reset_int)begin if (reset_int) begin byte_count_reg <= 0; end else begin byte_count_reg <= BYTE_COUNTER; endend//Use for determining the number of bytes in the dataalways @(posedge TX_CLK or posedge reset_int)begin if (reset_int) begin final_byte_count <= 0; end else if (load_CRC8) begin if (BYTE_COUNTER == 64) begin final_byte_count <= 60; end else begin final_byte_count <= byte_count_reg; end end else if (start_CRC8) begin final_byte_count <= final_byte_count + 1; endendalways @(posedge TX_CLK)begin if (transmit_pause_frame) begin byte_count_stat = 512; end else begin byte_count_stat = final_byte_count; endendalways @(posedge TX_CLK or posedge reset_int)begin if (reset_int) begin append_reg <= 0; load_final_CRC <= 0; append_end_frame <= 0; end else begin append_reg[0] <= load_CRC8; append_reg[9:1] <= append_reg[8:0]; load_final_CRC <= append_reg[9]; append_end_frame <= load_final_CRC; endend////always @(posedge TX_CLK or posedge reset_int)//begin// if (reset_int) begin// vlan_enabled_int <= 0;// end//end// VLAN field - 8100 at second 64 bit data at 32:47 and V1 V2 is at 48:63// length field at third 64 bit data at 0:15always @(posedge TX_CLK or posedge reset_int)begin if (reset_int) begin length_register <= 0; end else if (vlan_enabled_int & BYTE_COUNTER == 16) begin length_register <= TX_DATA_REG[15:0]; end else begin if (BYTE_COUNTER == 8) begin length_register <= TX_DATA_REG[47:32]; end end endalways @(posedge TX_CLK or posedge reset_int)begin if (reset_int) begin set_pause_stats <= 0; end else if (PAUSEVAL_DEL2) begin set_pause_stats <= 1; end else if (append_end_frame) begin set_pause_stats <= 0; endendendmodule?? 快捷鍵說明
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