always@(posedge rxclk or posedge reset)begin         if (reset)            da_addr <=#TP 0;         else if (start_da)            da_addr <=#TP rxd64_d1[47:0];         else           da_addr <=#TP da_addr;    end    //////////////////////////////////////    // Get Length/Type Field    //////////////////////////////////////    reg[15:0] lt_data;     always@(posedge rxclk or posedge reset)begin         if (reset)            lt_data <=#TP 0;         else if (start_lt)            lt_data <=#TP {rxd64_d1[39:32], rxd64_d1[47:40]};         else           lt_data <=#TP lt_data;    end     reg[5:0] pad_integer;    reg[5:0] pad_remain;    always@(posedge rxclk or posedge reset) begin         if (reset) begin           pad_integer <=#TP 0;           pad_remain <=#TP 0;         end         else begin           pad_integer <=#TP (lt_data[5:0] - 2)>>3;           pad_remain <=#TP lt_data[5:0] - 2;         end    end    //Remove PAD counter    reg[2:0] pad_cnt;    always@(posedge rxclk or posedge reset) begin         if (reset)           pad_cnt <=#TP 0;         else if(lt_data[5:0] == 1)           pad_cnt <=#TP 1;         else            pad_cnt <=#TP pad_integer[2:0] + 2;    end    reg [7:0] pad_last_rxc;       always@(posedge rxclk or posedge reset) begin         if (reset)           pad_last_rxc <=#TP 0;         else if(lt_data[5:0] == 1)           pad_last_rxc <=#TP 8'h7f;         else begin             case (pad_remain[2:0])                0: pad_last_rxc <=#TP 8'h00;                1: pad_last_rxc <=#TP 8'h01;                2: pad_last_rxc <=#TP 8'h03;                3: pad_last_rxc <=#TP 8'h07;                4: pad_last_rxc <=#TP 8'h0f;                5: pad_last_rxc <=#TP 8'h1f;                6: pad_last_rxc <=#TP 8'h3f;                7: pad_last_rxc <=#TP 8'h7f;             endcase       end    end         reg pad_frame;    always@(posedge rxclk or posedge reset) begin          if (reset)            pad_frame <=#TP 0;          else if(~(lt_data[0]|lt_data[1]|lt_data[2]|lt_data[3]|lt_data[4]|lt_data[5]))            pad_frame <=#TP 1'b0;          else if(lt_data<46)            pad_frame <=#TP 1'b1;          else            pad_frame <=#TP 1'b0;    end      //tagged frame indicator    always@(posedge rxclk or posedge reset) begin          if (reset)            tagged_frame <=#TP 1'b0;          else if (start_lt)            tagged_frame <=#TP (rxd64[63:32] == `TAG_SIGN);           else            tagged_frame <=#TP tagged_frame;    end    //pause frame indicator    always@(posedge rxclk or posedge reset) begin          if (reset)            pause_frame <=#TP 1'b0;          else if (start_lt)            pause_frame <=#TP (rxd64[47:32] == `PAUSE_SIGN);           else             pause_frame <=#TP 1'b0;    end    /////////////////////////////////////////////    // Generate proper rxc to FIFO						    /////////////////////////////////////////////    reg [7:0]rxc_final;    wire [7:0]rxc_fifo; //rxc send to fifo        always@(posedge rxclk or posedge reset) begin         if (reset)           rxc_final <=#TP 0;         else if (get_terminator & this_cycle)           rxc_final <=#TP rxc_end_data;         else if (get_terminator_d1 & ~this_cycle)           rxc_final <=#TP rxc_end_data;         else if (get_error_code)           rxc_final <=#TP 0;          else if (receiving)             rxc_final <=#TP `ALLONES8;         else             rxc_final <=#TP 0;     end     assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;      ////////////////////////////////////////////////////////////////    // FIFO management, to generate rx_good_frame/rx_bad_frame    // after a frame has been totally received.    ////////////////////////////////////////////////////////////////    wire rxfifo_full;    wire rxfifo_empty;    wire fifo_wr_en;    wire [63:0] rx_data_tmp;    wire [7:0] rx_data_valid_tmp;       reg fifo_rd_en;    reg[1:0] fifo_state;    wire rx_good_frame;    wire rx_bad_frame;    reg check_reset;    always@(posedge rxclk or posedge reset) begin         if(reset) begin           fifo_rd_en <=#TP 1'b0;           fifo_state <=#TP IDLE;           check_reset <=#TP 1'b0;         end         else             case (fifo_state)                  IDLE: begin                      check_reset <=#TP 1'b0;                      fifo_state <=#TP IDLE;                      fifo_rd_en <=#TP 1'b0;                      if(~rxfifo_empty) begin                           fifo_rd_en <=#TP 1'b1;                         fifo_state <=#TP WAIT_TMP;                      end                   end                 READ: begin                      check_reset <=#TP 1'b0;                      fifo_rd_en <=#TP 1'b1;                      fifo_state <=#TP READ;                      if(rx_data_valid_tmp!=8'hff) begin                         fifo_state <=#TP WAIT;                         fifo_rd_en <=#TP 1'b0;                      end                 end                   WAIT_TMP: begin                      if(rx_data_valid_tmp == 8'hff)                         fifo_state <=#TP READ;                      else                          fifo_state <=#TP WAIT_TMP;                 end                   WAIT: begin                      fifo_state <=#TP WAIT;                      check_reset <=#TP 1'b0;                      fifo_rd_en <=#TP 1'b0;                      if(bad_frame_get | good_frame_get)begin                         fifo_state <=#TP IDLE;                         check_reset <=#TP 1'b1;                      end                   end             endcase    end     reg[2:0] pad_cnt_reg;    always@(posedge rxclk or posedge reset) begin         if(reset)           pad_cnt_reg <=#TP 0;         else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)           pad_cnt_reg <=#TP pad_cnt;         else if(pad_cnt_reg ==0)           pad_cnt_reg <=#TP 0;         else if(fifo_state[1])           pad_cnt_reg <=#TP pad_cnt_reg-1;         else           pad_cnt_reg <=#TP 0;    end     reg[7:0] pad_rxc_reg;    always@(posedge rxclk or posedge reset)begin         if(reset)           pad_rxc_reg <=#TP 0;         else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)           pad_rxc_reg <=#TP pad_last_rxc;         else           pad_rxc_reg <=#TP pad_rxc_reg;    end     reg pad_frame_d1;    always@(posedge rxclk or posedge reset) begin         if(reset)           pad_frame_d1<=#TP 1'b0;         else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)           pad_frame_d1<=#TP 1'b1;         else if(fifo_state == WAIT)            pad_frame_d1 <=#TP 1'b0;         else           pad_frame_d1 <=#TP pad_frame_d1;     end         assign rx_good_frame = good_frame_get & (fifo_state == WAIT);    assign rx_bad_frame = bad_frame_get & (fifo_state == WAIT);        assign fifo_wr_en = receiving_d2;        defparam rxdatain.pWordWidth = 64;    defparam rxdatain.pDepthWidth = 7;    SwitchSyncFIFO rxdatain(	.nReset(!reset),	.iClk(rxclk),	.iWEn(fifo_wr_en),	.ivDataIn(rxd64_d3),	.iREn(fifo_rd_en),	.ovDataOut(rx_data_tmp),	.qEmpty(rxfifo_empty),	.qFull(rxfifo_full),	.qvCount()    );    defparam rxcntrlin.pWordWidth = 8;    defparam rxcntrlin.pDepthWidth = 7;    SwitchSyncFIFO rxcntrlin(	.nReset(!reset),	.iClk(rxclk),	.iWEn(fifo_wr_en),	.ivDataIn(rxc_fifo),	.iREn(fifo_rd_en),	.ovDataOut(rx_data_valid_tmp),	.qEmpty(),	.qFull(),	.qvCount()    );    reg [63:0] rx_data;    always@(posedge rxclk or posedge reset) begin         if (reset) begin            rx_data <=#TP 0;         end         else begin            rx_data <=#TP rx_data_tmp;         end    end     reg [7:0] rx_data_valid;    always@(posedge rxclk or posedge reset) begin         if (reset)            rx_data_valid <=#TP 0;         else if(fifo_state[1] & pad_frame_d1)            if(pad_cnt_reg==1)               rx_data_valid <=#TP pad_rxc_reg;            else if(pad_cnt_reg==0)               rx_data_valid <=#TP 0;            else               rx_data_valid <=#TP rx_data_valid_tmp;           else if(fifo_state[1] & ~pad_frame_d1)             rx_data_valid <=#TP rx_data_valid_tmp;           else            rx_data_valid <=#TP 0;    end endmodule