library ieee;
use ieee. std_logic_1164. all;
use ieee. std_logic_arith. all;
use ieee. std_logic_unsigned. all;
entity CICfive is
　port (clk :in std_logic ;
　　　din :in std_logic_vector (7 downto 0);
　　　clk2 :out std_logic ;
　　　dout :out std_logic_vector (9 downto 0) ) ;
end entity CICfive ;
architecture huarui of CICfive is
　type state_type is (hold ,sample);
　signal state : state_type ;
　signal count :integer range 0 to 24 ;
　signal temp : std_logic_vector (7 downto 0) ;
　signal sxtx : std_logic_vector (31 downto 0) ;
　signal i0 ,i1 ,i2 ,i3 ,i4 : std_logic_vector (31 downto 0) ;
　signal i2d1 ,i2d2 ,c1 ,c0 : std_logic_vector (31 downto 0) ;
　signal c1d1 ,c1d2 ,c2 : std_logic_vector (31 downto 0) ;
　signal c2d1 ,c2d2 ,c3 : std_logic_vector (31 downto 0) ;
　signal c3d1 ,c3d2 ,c4 : std_logic_vector (31 downto 0) ;
　signal c4d1 ,c4d2 ,c5 : std_logic_vector (31 downto 0) ;
begin
　FSM:process
　begin
　wait until clk =‘1’;
　　if count = 24 then
　　　 count < = 0 ;
　　　 state < = sample ;
　　　 clk2 < =‘1’;
　　else
　　　 count < = count + 1 ;
　　　 state < = hold ;
　　　 clk2 < =‘0’;
　　end if ;
　　end process FSM;
sxt :process (temp)
　　begin
　　sxtx (7 downto 0) < = temp ;
　　for k in 31 downto 8 loop
　　　sxtx (k) < = temp (temp’high) ;
　　end loop ;
　　end process sxt ;
　int :process
　begin
　wait until clk =‘1 ’;
　temp < = din ;
　i0 < = i0 + conv_integer ( sxtx) ;
　i1 < = i1 + i0 ;
　i2 < = i2 + i1 ;
　i3 < = i3 + i2 ;
　i4 < = i4 + i3 ;
　end process int ;
　comb :process
　begin
  　wait until clk =‘1’;
　if state = sample then
　　c0 < = i4 ;
　　i2d1 < = c0 ;
　　i2d2 < = i2d1 ;
　　c1 < = c0 - i2d2 ;
　　c1d1 < = c1 ;
　　c1d2 < = c1d1 ;
　　c2 < = c1 - c1d2 ;
　　c2d1 < = c2 ;
　　c2d2 < = c2d1 ;
　　c3 < = c2 - c2d2 ;
　　c3d1 < = c3 ;
　　c3d2 < = c3d1 ;
　　c4 < = c3 - c3d2 ;
　　c4d1 < = c4 ;
　　c4d2 < = c4d1 ;
　　c5 < = c4 - c4d2 ;
　end if ;
　end process comb ;
　dout < = c5 (9 downto 0) ;
　end architecture huarui