?? stator_u.mdl
字號:
Model {
Name "stator_u"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Sun Oct 19 11:53:24 2003"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "pxs"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Thu Jan 01 21:32:57 2004"
ModelVersionFormat "1.%<AutoIncrement:6>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
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StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
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ParameterPooling on
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ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
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BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
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FontWeight "normal"
FontAngle "normal"
ShowName on
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Block {
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VectorParams1D on
ShowAdditionalParam off
OutDataTypeMode "Inherit from 'Constant value'"
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ConRadixGroup "Use specified scaling"
OutScaling "2^0"
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Block {
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Multiplication "Element-wise(K.*u)"
ShowAdditionalParam off
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
SampleTime "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
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Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
ZeroCross on
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Block {
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
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Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
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RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
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Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
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AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
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LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
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System {
Name "stator_u"
Location [2, 74, 1014, 724]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Inport
Name "uqs"
Position [280, 223, 310, 237]
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Block {
BlockType Inport
Name "iqs"
Position [280, 253, 310, 267]
Port "2"
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Block {
BlockType Inport
Name "uds"
Position [280, 283, 310, 297]
Port "3"
}
Block {
BlockType Inport
Name "ids"
Position [280, 313, 310, 327]
Port "4"
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Block {
BlockType SubSystem
Name "Subsystem"
Ports [4, 2]
Position [360, 216, 405, 334]
TreatAsAtomicUnit off
System {
Name "Subsystem"
Location [207, 116, 602, 579]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "uqs"
Position [115, 303, 145, 317]
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Block {
BlockType Inport
Name "iqs"
Position [90, 328, 120, 342]
Port "2"
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Block {
BlockType Inport
Name "uds"
Position [70, 143, 100, 157]
Port "3"
}
Block {
BlockType Inport
Name "ids"
Position [105, 163, 135, 177]
Port "4"
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [265, 285, 295, 315]
}
Block {
BlockType Integrator
Name "Integrator1"
Ports [1, 1]
Position [250, 150, 280, 180]
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [95, 191, 120, 204]
InputSameDT off
}
Block {
BlockType Product
Name "Product1"
Ports [2, 1]
Position [95, 276, 120, 294]
ShowName off
InputSameDT off
}
Block {
BlockType Sum
Name "Sum"
Ports [3, 1]
Position [200, 249, 245, 346]
ShowName off
Inputs "|-+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum1"
Ports [3, 1]
Position [195, 115, 235, 210]
ShowName off
Inputs "|+-+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Gain
Name "rs"
Position [155, 166, 180, 184]
}
Block {
BlockType Gain
Name "rs1"
Position [155, 326, 185, 344]
}
Block {
BlockType Constant
Name "ws"
Position [25, 218, 55, 242]
}
Block {
BlockType Outport
Name "psiqs"
Position [325, 293, 355, 307]
}
Block {
BlockType Outport
Name "psids"
Position [325, 158, 355, 172]
Port "2"
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Line {
SrcBlock "rs1"
SrcPort 1
DstBlock "Sum"
DstPort 3
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Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Integrator"
DstPort 1
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Line {
SrcBlock "Integrator"
SrcPort 1
Points [20, 0; -5, 0]
Branch {
DstBlock "psiqs"
DstPort 1
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Branch {
Points [-10, 0; 0, -80; -225, 0]
DstBlock "Product"
DstPort 2
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Line {
SrcBlock "uqs"
SrcPort 1
DstBlock "Sum"
DstPort 2
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Line {
SrcBlock "iqs"
SrcPort 1
DstBlock "rs1"
DstPort 1
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Line {
SrcBlock "rs"
SrcPort 1
DstBlock "Sum1"
DstPort 2
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Line {
SrcBlock "Sum1"
SrcPort 1
DstBlock "Integrator1"
DstPort 1
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Line {
SrcBlock "Integrator1"
SrcPort 1
Points [20, 0; 0, 0]
Branch {
DstBlock "psids"
DstPort 1
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Branch {
Points [0, 0; -10, 0; 0, 75; -215, 0]
DstBlock "Product1"
DstPort 1
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Line {
SrcBlock "uds"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "ids"
SrcPort 1
DstBlock "rs"
DstPort 1
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Line {
SrcBlock "ws"
SrcPort 1
Points [10, 0]
Branch {
Points [0, -35]
DstBlock "Product"
DstPort 1
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Branch {
Points [0, 60]
DstBlock "Product1"
DstPort 2
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Line {
SrcBlock "Product1"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Sum1"
DstPort 3
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}
}
Block {
BlockType Outport
Name "psiqs"
Position [445, 238, 475, 252]
}
Block {
BlockType Outport
Name "psids"
Position [445, 298, 475, 312]
Port "2"
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Line {
SrcBlock "Subsystem"
SrcPort 1
DstBlock "psiqs"
DstPort 1
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Line {
SrcBlock "Subsystem"
SrcPort 2
DstBlock "psids"
DstPort 1
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Line {
SrcBlock "uqs"
SrcPort 1
DstBlock "Subsystem"
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Line {
SrcBlock "iqs"
SrcPort 1
DstBlock "Subsystem"
DstPort 2
}
Line {
SrcBlock "uds"
SrcPort 1
DstBlock "Subsystem"
DstPort 3
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Line {
SrcBlock "ids"
SrcPort 1
DstBlock "Subsystem"
DstPort 4
}
Annotation {
Name "定子電壓模塊"
Position [427, 541]
}
}
}
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