/* * $Id: quirks.c,v 1.5 1998/05/02 19:24:14 mj Exp $ * *  This file contains work-arounds for many known PCI hardware *  bugs.  Devices present only on certain architectures (host *  bridges et cetera) should be handled in arch-specific code. * *  Copyright (c) 1999 Martin Mares <mj@ucw.cz> * *  The bridge optimization stuff has been removed. If you really *  have a silly BIOS which is unable to set your host bridge right, *  use the PowerTweak utility (see http://powertweak.sourceforge.net). */#include <linux/config.h>#include <linux/types.h>#include <linux/kernel.h>#include <linux/pci.h>#include <linux/init.h>#include <linux/delay.h>#undef DEBUG/* Deal with broken BIOS'es that neglect to enable passive release,   which can cause problems in combination with the 82441FX/PPro MTRRs */static void __init quirk_passive_release(struct pci_dev *dev){	struct pci_dev *d = NULL;	unsigned char dlc;	/* We have to make sure a particular bit is set in the PIIX3	   ISA bridge, so we have to go out and find it. */	while ((d = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {		pci_read_config_byte(d, 0x82, &dlc);		if (!(dlc & 1<<1)) {			printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", d->slot_name);			dlc |= 1<<1;			pci_write_config_byte(d, 0x82, dlc);		}	}}/*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround    but VIA don't answer queries. If you happen to have good contacts at VIA    ask them for me please -- Alan         This appears to be BIOS not version dependent. So presumably there is a     chipset level fix */    int isa_dma_bridge_buggy;		/* Exported */    static void __init quirk_isa_dma_hangs(struct pci_dev *dev){	if (!isa_dma_bridge_buggy) {		isa_dma_bridge_buggy=1;		printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");	}}int pci_pci_problems;/* *	Chipsets where PCI->PCI transfers vanish or hang */static void __init quirk_nopcipci(struct pci_dev *dev){	if((pci_pci_problems&PCIPCI_FAIL)==0)	{		printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");		pci_pci_problems|=PCIPCI_FAIL;	}}/* *	Triton requires workarounds to be used by the drivers */ static void __init quirk_triton(struct pci_dev *dev){	if((pci_pci_problems&PCIPCI_TRITON)==0)	{		printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");		pci_pci_problems|=PCIPCI_TRITON;	}}/* *	VIA Apollo KT133 needs PCI latency patch *	Made according to a windows driver based patch by George E. Breese *	see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm *      Also see http://home.tiscalinet.de/au-ja/review-kt133a-1-en.html for *      the info on which Mr Breese based his work. * *	Updated based on further information from the site and also on *	information provided by VIA  */static void __init quirk_vialatency(struct pci_dev *dev){	struct pci_dev *p;	u8 rev;	u8 busarb;	/* Ok we have a potential problem chipset here. Now see if we have	   a buggy southbridge */	   	p=pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);	if(p!=NULL)	{		pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);		/* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */		/* Check for buggy part revisions */		if (rev < 0x40 || rev > 0x42) 			return;	}	else	{		p = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);		if(p==NULL)	/* No problem parts */			return;		pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);		/* Check for buggy part revisions */		if (rev < 0x10 || rev > 0x12) 			return;	}		/*	 *	Ok we have the problem. Now set the PCI master grant to 	 *	occur every master grant. The apparent bug is that under high	 *	PCI load (quite common in Linux of course) you can get data	 *	loss when the CPU is held off the bus for 3 bus master requests	 *	This happens to include the IDE controllers....	 *	 *	VIA only apply this fix when an SB Live! is present but under	 *	both Linux and Windows this isnt enough, and we have seen	 *	corruption without SB Live! but with things like 3 UDMA IDE	 *	controllers. So we ignore that bit of the VIA recommendation..	 */	pci_read_config_byte(dev, 0x76, &busarb);	/* Set bit 4 and bi 5 of byte 76 to 0x01 	   "Master priority rotation on every PCI master grant */	busarb &= ~(1<<5);	busarb |= (1<<4);	pci_write_config_byte(dev, 0x76, busarb);	printk(KERN_INFO "Applying VIA southbridge workaround.\n");}/* *	VIA Apollo VP3 needs ETBF on BT848/878 */ static void __init quirk_viaetbf(struct pci_dev *dev){	if((pci_pci_problems&PCIPCI_VIAETBF)==0)	{		printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");		pci_pci_problems|=PCIPCI_VIAETBF;	}}static void __init quirk_vsfx(struct pci_dev *dev){	if((pci_pci_problems&PCIPCI_VSFX)==0)	{		printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");		pci_pci_problems|=PCIPCI_VSFX;	}}/* *	Natoma has some interesting boundary conditions with Zoran stuff *	at least */ static void __init quirk_natoma(struct pci_dev *dev){	if((pci_pci_problems&PCIPCI_NATOMA)==0)	{		printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");		pci_pci_problems|=PCIPCI_NATOMA;	}}/* *  S3 868 and 968 chips report region size equal to 32M, but they decode 64M. *  If it's needed, re-allocate the region. */static void __init quirk_s3_64M(struct pci_dev *dev){	struct resource *r = &dev->resource[0];	if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {		r->start = 0;		r->end = 0x3ffffff;	}}static void __init quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr){	region &= ~(size-1);	if (region) {		struct resource *res = dev->resource + nr;		res->name = dev->name;		res->start = region;		res->end = region + size - 1;		res->flags = IORESOURCE_IO;		pci_claim_resource(dev, nr);	}}	/* * Let's make the southbridge information explicit instead * of having to worry about people probing the ACPI areas, * for example.. (Yes, it happens, and if you read the wrong * ACPI register it will put the machine to sleep with no * way of waking it up again. Bummer). * * ALI M7101: Two IO regions pointed to by words at *	0xE0 (64 bytes of ACPI registers) *	0xE2 (32 bytes of SMB registers) */static void __init quirk_ali7101_acpi(struct pci_dev *dev){	u16 region;	pci_read_config_word(dev, 0xE0, &region);	quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);	pci_read_config_word(dev, 0xE2, &region);	quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);}/* * PIIX4 ACPI: Two IO regions pointed to by longwords at *	0x40 (64 bytes of ACPI registers) *	0x90 (32 bytes of SMB registers) */static void __init quirk_piix4_acpi(struct pci_dev *dev){	u32 region;	pci_read_config_dword(dev, 0x40, &region);	quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);	pci_read_config_dword(dev, 0x90, &region);	quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);}/* * VIA ACPI: One IO region pointed to by longword at *	0x48 or 0x20 (256 bytes of ACPI registers) */static void __init quirk_vt82c586_acpi(struct pci_dev *dev){	u8 rev;	u32 region;	pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);	if (rev & 0x10) {		pci_read_config_dword(dev, 0x48, &region);		region &= PCI_BASE_ADDRESS_IO_MASK;		quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);	}}/* * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at *	0x48 (256 bytes of ACPI registers)