extern void ide_init_slc90e66(ide_hwif_t *);#define PCI_SLC90E66	&pci_init_slc90e66#define ATA66_SLC90E66	&ata66_slc90e66#define INIT_SLC90E66	&ide_init_slc90e66#else#define PCI_SLC90E66	NULL#define ATA66_SLC90E66	NULL#define INIT_SLC90E66	NULL#endif#ifdef CONFIG_BLK_DEV_SL82C105extern unsigned int pci_init_sl82c105(struct pci_dev *, const char *);extern void dma_init_sl82c105(ide_hwif_t *, unsigned long);extern void ide_init_sl82c105(ide_hwif_t *);#define PCI_W82C105	&pci_init_sl82c105#define DMA_W82C105	&dma_init_sl82c105#define INIT_W82C105	&ide_init_sl82c105#else#define PCI_W82C105	NULL#define DMA_W82C105	NULL#define INIT_W82C105	IDE_IGNORE#endif#ifdef CONFIG_BLK_DEV_TRM290extern void ide_init_trm290(ide_hwif_t *);#define INIT_TRM290	&ide_init_trm290#else#define INIT_TRM290	IDE_IGNORE#endif#ifdef CONFIG_BLK_DEV_VIA82CXXXextern unsigned int pci_init_via82cxxx(struct pci_dev *, const char *);extern unsigned int ata66_via82cxxx(ide_hwif_t *);extern void ide_init_via82cxxx(ide_hwif_t *);extern void ide_dmacapable_via82cxxx(ide_hwif_t *, unsigned long);#define PCI_VIA82CXXX	&pci_init_via82cxxx#define ATA66_VIA82CXXX	&ata66_via82cxxx#define INIT_VIA82CXXX	&ide_init_via82cxxx#define DMA_VIA82CXXX	&ide_dmacapable_via82cxxx#else#define PCI_VIA82CXXX	NULL#define ATA66_VIA82CXXX	NULL#define INIT_VIA82CXXX	NULL#define DMA_VIA82CXXX	NULL#endiftypedef struct ide_pci_enablebit_s {	byte	reg;	/* byte pci reg holding the enable-bit */	byte	mask;	/* mask to isolate the enable-bit */	byte	val;	/* value of masked reg when "enabled" */} ide_pci_enablebit_t;typedef struct ide_pci_device_s {	ide_pci_devid_t		devid;	char			*name;	unsigned int		(*init_chipset)(struct pci_dev *dev, const char *name);	unsigned int		(*ata66_check)(ide_hwif_t *hwif);	void 			(*init_hwif)(ide_hwif_t *hwif);	void			(*dma_init)(ide_hwif_t *hwif, unsigned long dmabase);	ide_pci_enablebit_t	enablebits[2];	byte			bootable;	unsigned int		extra;} ide_pci_device_t;static ide_pci_device_t ide_pci_chipsets[] __initdata = {	{DEVID_PIIXa,	"PIIX",		NULL,		NULL,		INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}}, 	ON_BOARD,	0 },	{DEVID_PIIXb,	"PIIX",		NULL,		NULL,		INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}}, 	ON_BOARD,	0 },	{DEVID_MPIIX,	"MPIIX",	NULL,		NULL,		INIT_PIIX,	NULL,		{{0x6D,0x80,0x80}, {0x6F,0x80,0x80}},	ON_BOARD,	0 },	{DEVID_PIIX3,	"PIIX3",	PCI_PIIX,	NULL,		INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}}, 	ON_BOARD,	0 },	{DEVID_PIIX4,	"PIIX4",	PCI_PIIX,	NULL,		INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}}, 	ON_BOARD,	0 },	{DEVID_PIIX4E,	"PIIX4",	PCI_PIIX,	NULL,		INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}},	ON_BOARD,	0 },	{DEVID_PIIX4E2,	"PIIX4",	PCI_PIIX,	NULL,		INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}},	ON_BOARD,	0 },	{DEVID_PIIX4U,	"PIIX4",	PCI_PIIX,	ATA66_PIIX,	INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}},	ON_BOARD,	0 },	{DEVID_PIIX4U2,	"PIIX4",	PCI_PIIX,	ATA66_PIIX,	INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}},	ON_BOARD,	0 },	{DEVID_PIIX4NX,	"PIIX4",	PCI_PIIX,	NULL,		INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}},	ON_BOARD,	0 },	{DEVID_PIIX4U3,	"PIIX4",	PCI_PIIX,	ATA66_PIIX,	INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}},	ON_BOARD,	0 },	{DEVID_PIIX4U4, "PIIX4",	PCI_PIIX,	ATA66_PIIX,	INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}},	ON_BOARD,	0 },	{DEVID_PIIX4U5, "PIIX4",	PCI_PIIX,	ATA66_PIIX,	INIT_PIIX,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}},	ON_BOARD,	0 },	{DEVID_VIA_IDE,	"VIA_IDE",	NULL,		NULL,		NULL,		NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_MR_IDE,	"VP_IDE",	PCI_VIA82CXXX,	ATA66_VIA82CXXX,INIT_VIA82CXXX,	DMA_VIA82CXXX,	{{0x40,0x02,0x02}, {0x40,0x01,0x01}}, 	ON_BOARD,	0 },	{DEVID_VP_IDE,	"VP_IDE",	PCI_VIA82CXXX,	ATA66_VIA82CXXX,INIT_VIA82CXXX,	DMA_VIA82CXXX,	{{0x40,0x02,0x02}, {0x40,0x01,0x01}}, 	ON_BOARD,	0 },#ifdef CONFIG_PDC202XX_FORCE        {DEVID_PDC20246,"PDC20246",	PCI_PDC202XX,	NULL,		INIT_PDC202XX,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	OFF_BOARD,	16 },        {DEVID_PDC20262,"PDC20262",	PCI_PDC202XX,	ATA66_PDC202XX,	INIT_PDC202XX,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	OFF_BOARD,	48 },        {DEVID_PDC20265,"PDC20265",	PCI_PDC202XX,	ATA66_PDC202XX,	INIT_PDC202XX,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	OFF_BOARD,	48 },        {DEVID_PDC20267,"PDC20267",	PCI_PDC202XX,	ATA66_PDC202XX,	INIT_PDC202XX,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	OFF_BOARD,	48 },#else /* !CONFIG_PDC202XX_FORCE */	{DEVID_PDC20246,"PDC20246",	PCI_PDC202XX,	NULL,		INIT_PDC202XX,	NULL,		{{0x50,0x02,0x02}, {0x50,0x04,0x04}}, 	OFF_BOARD,	16 },	{DEVID_PDC20262,"PDC20262",	PCI_PDC202XX,	ATA66_PDC202XX,	INIT_PDC202XX,	NULL,		{{0x50,0x02,0x02}, {0x50,0x04,0x04}},	OFF_BOARD,	48 },	{DEVID_PDC20265,"PDC20265",	PCI_PDC202XX,	ATA66_PDC202XX,	INIT_PDC202XX,	NULL,		{{0x50,0x02,0x02}, {0x50,0x04,0x04}},	OFF_BOARD,	48 },	{DEVID_PDC20267,"PDC20267",	PCI_PDC202XX,	ATA66_PDC202XX,	INIT_PDC202XX,	NULL,		{{0x50,0x02,0x02}, {0x50,0x04,0x04}},	OFF_BOARD,	48 },#endif	{DEVID_PDC20268,"PDC20268",	PCI_PDC202XX,	ATA66_PDC202XX,	INIT_PDC202XX,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	OFF_BOARD,	16 },	/* Promise used a different PCI ident for the raid card apparently to try and	   prevent Linux detecting it and using our own raid code. We want to detect	   it for the ataraid drivers, so we have to list both here.. */	{DEVID_PDC20268R,"PDC20268",	PCI_PDC202XX,	ATA66_PDC202XX,	INIT_PDC202XX,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	OFF_BOARD,	16 },	{DEVID_RZ1000,	"RZ1000",	NULL,		NULL,		INIT_RZ1000,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 	ON_BOARD,	0 },	{DEVID_RZ1001,	"RZ1001",	NULL,		NULL,		INIT_RZ1000,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 	ON_BOARD,	0 },	{DEVID_SAMURAI,	"SAMURAI",	NULL,		NULL,		INIT_SAMURAI,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_CMD640,	"CMD640",	NULL,		NULL,		IDE_IGNORE,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 	ON_BOARD,	0 },	{DEVID_NS87410,	"NS87410",	NULL,		NULL,		NULL,		NULL,		{{0x43,0x08,0x08}, {0x47,0x08,0x08}}, 	ON_BOARD,	0 },	{DEVID_SIS5513,	"SIS5513",	PCI_SIS5513,	ATA66_SIS5513,	INIT_SIS5513,	NULL,		{{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 	ON_BOARD,	0 },	{DEVID_CMD643,	"CMD643",	PCI_CMD64X,	NULL,		INIT_CMD64X,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_CMD646,	"CMD646",	PCI_CMD64X,	NULL,		INIT_CMD64X,	NULL,		{{0x00,0x00,0x00}, {0x51,0x80,0x80}}, 	ON_BOARD,	0 },	{DEVID_CMD648,	"CMD648",	PCI_CMD64X,	ATA66_CMD64X,	INIT_CMD64X,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_CMD649,	"CMD649",	PCI_CMD64X,	ATA66_CMD64X,	INIT_CMD64X,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_HT6565,	"HT6565",	NULL,		NULL,		NULL,		NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 	ON_BOARD,	0 },	{DEVID_OPTI621,	"OPTI621",	NULL,		NULL,		INIT_OPTI621,	NULL,		{{0x45,0x80,0x00}, {0x40,0x08,0x00}}, 	ON_BOARD,	0 },	{DEVID_OPTI621X,"OPTI621X",	NULL,		NULL,		INIT_OPTI621,	NULL,		{{0x45,0x80,0x00}, {0x40,0x08,0x00}}, 	ON_BOARD,	0 },	{DEVID_TRM290,	"TRM290",	NULL,		NULL,		INIT_TRM290,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 	ON_BOARD,	0 },	{DEVID_NS87415,	"NS87415",	NULL,		NULL,		INIT_NS87415,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 	ON_BOARD,	0 },	{DEVID_AEC6210,	"AEC6210",	PCI_AEC62XX,	NULL,		INIT_AEC62XX,	DMA_AEC62XX,	{{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 	OFF_BOARD,	0 },	{DEVID_AEC6260,	"AEC6260",	PCI_AEC62XX,	ATA66_AEC62XX,	INIT_AEC62XX,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	NEVER_BOARD,	0 },	{DEVID_AEC6260R,"AEC6260R",	PCI_AEC62XX,	ATA66_AEC62XX,	INIT_AEC62XX,	NULL,		{{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},	OFF_BOARD,	0 },	{DEVID_W82C105,	"W82C105",	PCI_W82C105,	NULL,		INIT_W82C105,	DMA_W82C105,	{{0x40,0x01,0x01}, {0x40,0x10,0x10}}, 	ON_BOARD,	0 },	{DEVID_UM8673F,	"UM8673F",	NULL,		NULL,		NULL,		NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_UM8886A,	"UM8886A",	NULL,		NULL,		NULL,		NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_UM8886BF,"UM8886BF",	NULL,		NULL,		NULL,		NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 	ON_BOARD,	0 },	{DEVID_HPT34X,	"HPT34X",	PCI_HPT34X,	NULL,		INIT_HPT34X,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	NEVER_BOARD,	16 },	{DEVID_HPT366,	"HPT366",	PCI_HPT366,	ATA66_HPT366,	INIT_HPT366,	DMA_HPT366,	{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	OFF_BOARD,	240 },	{DEVID_ALI15X3,	"ALI15X3",	PCI_ALI15X3,	ATA66_ALI15X3,	INIT_ALI15X3,	DMA_ALI15X3,	{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_CY82C693,"CY82C693",	PCI_CY82C693,	NULL,		INIT_CY82C693,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_HINT,	"HINT_IDE",	NULL,		NULL,		NULL,		NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_CS5530,	"CS5530",	PCI_CS5530,	NULL,		INIT_CS5530,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_AMD7401,	"AMD7401",	NULL,		NULL,		NULL,		NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_AMD7409,	"AMD7409",	PCI_AMD74XX,	ATA66_AMD74XX,	INIT_AMD74XX,	DMA_AMD74XX,	{{0x40,0x01,0x01}, {0x40,0x02,0x02}},	ON_BOARD,	0 },	{DEVID_AMD7411,	"AMD7411",	PCI_AMD74XX,	ATA66_AMD74XX,	INIT_AMD74XX,	DMA_AMD74XX,	{{0x40,0x01,0x01}, {0x40,0x02,0x02}},	ON_BOARD,	0 },	{DEVID_PDCADMA,	"PDCADMA",	PCI_PDCADMA,	ATA66_PDCADMA,	INIT_PDCADMA,	DMA_PDCADMA,	{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	OFF_BOARD,	0 },	{DEVID_SLC90E66,"SLC90E66",	PCI_SLC90E66,	ATA66_SLC90E66,	INIT_SLC90E66,	NULL,		{{0x41,0x80,0x80}, {0x43,0x80,0x80}},	ON_BOARD,	0 },        {DEVID_OSB4,    "ServerWorks OSB4",		PCI_SVWKS,	ATA66_SVWKS,	INIT_SVWKS,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_CSB5,	"ServerWorks CSB5",		PCI_SVWKS,	ATA66_SVWKS,	INIT_SVWKS,	NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}},	ON_BOARD,	0 },	{DEVID_ITE8172G,"IT8172G",	PCI_IT8172,	NULL,	INIT_IT8172,	NULL,		{{0x00,0x00,0x00}, {0x40,0x00,0x01}},	ON_BOARD,	0 },	{IDE_PCI_DEVID_NULL, "PCI_IDE",	NULL,		NULL,		NULL,		NULL,		{{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 	ON_BOARD,	0 }};/* * This allows offboard ide-pci cards the enable a BIOS, verify interrupt * settings of split-mirror pci-config space, place chipset into init-mode, * and/or preserve an interrupt if the card is not native ide support. */static unsigned int __init ide_special_settings (struct pci_dev *dev, const char *name){	switch(dev->device) {		case PCI_DEVICE_ID_TTI_HPT366:		case PCI_DEVICE_ID_PROMISE_20246:		case PCI_DEVICE_ID_PROMISE_20262:		case PCI_DEVICE_ID_PROMISE_20265:		case PCI_DEVICE_ID_PROMISE_20267:		case PCI_DEVICE_ID_PROMISE_20268:		case PCI_DEVICE_ID_ARTOP_ATP850UF:		case PCI_DEVICE_ID_ARTOP_ATP860:		case PCI_DEVICE_ID_ARTOP_ATP860R:			return dev->irq;		default:			break;	}	return 0;}/* * Match a PCI IDE port against an entry in ide_hwifs[], * based on io_base port if possible. */static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable, const char *name){	int h;	ide_hwif_t *hwif;	/*	 * Look for a hwif with matching io_base specified using	 * parameters to ide_setup().	 */	for (h = 0; h < MAX_HWIFS; ++h) {		hwif = &ide_hwifs[h];		if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {			if (hwif->chipset == ide_generic)				return hwif; /* a perfect match */		}	}	/*	 * Look for a hwif with matching io_base default value.	 * If chipset is "ide_unknown", then claim that hwif slot.	 * Otherwise, some other chipset has already claimed it..  :(	 */	for (h = 0; h < MAX_HWIFS; ++h) {		hwif = &ide_hwifs[h];		if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {			if (hwif->chipset == ide_unknown)				return hwif; /* match */			printk("%s: port 0x%04lx already claimed by %s\n", name, io_base, hwif->name);			return NULL;	/* already claimed */		}	}	/*	 * Okay, there is no hwif matching our io_base,	 * so we'll just claim an unassigned slot.	 * Give preference to claiming other slots before claiming ide0/ide1,	 * just in case there's another interface yet-to-be-scanned	 * which uses ports 1f0/170 (the ide0/ide1 defaults).	 *	 * Unless there is a bootable card that does not use the standard	 * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag.	 */	if (bootable) {		for (h = 0; h < MAX_HWIFS; ++h) {			hwif = &ide_hwifs[h];			if (hwif->chipset == ide_unknown)				return hwif;	/* pick an unused entry */		}	} else {		for (h = 2; h < MAX_HWIFS; ++h) {			hwif = ide_hwifs + h;			if (hwif->chipset == ide_unknown)				return hwif;	/* pick an unused entry */		}	}	for (h = 0; h < 2; ++h) {		hwif = ide_hwifs + h;		if (hwif->chipset == ide_unknown)			return hwif;	/* pick an unused entry */	}	printk("%s: too many IDE interfaces, no room in table\n", name);	return NULL;}static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name){	byte reg, progif = 0;	/*	 * Place both IDE interfaces into PCI "native" mode:	 */	if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {		if ((progif & 0xa) != 0xa) {			printk("%s: device not capable of full native PCI mode\n", name);			return 1;		}		printk("%s: placing both ports into native PCI mode\n", name);		(void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);		if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {			printk("%s: rewrite of PROGIF failed, wanted 0x%04x, got 0x%04x\n", name, progif|5, progif);			return 1;		}	}	/*	 * Setup base registers for IDE command/control spaces for each interface:	 */	for (reg = 0; reg < 4; reg++) {		struct resource *res = dev->resource + reg;		if ((res->flags & IORESOURCE_IO) == 0)			continue;		if (!res->start) {			printk("%s: Missing I/O address #%d\n", name, reg);			return 1;		}	}	return 0;}/* * ide_setup_pci_device() looks at the primary/secondary interfaces * on a PCI IDE device and, if they are enabled, prepares the IDE driver * for use with them.  This generic code works for most PCI chipsets. * * One thing that is not standardized is the location of the * primary/secondary interface "enable/disable" bits.  For chipsets that * we "know" about, this information is in the ide_pci_device_t struct; * for all other chipsets, we just assume both interfaces are enabled. */static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d){	unsigned int port, at_least_one_hwif_enabled = 0, autodma = 0, pciirq = 0;	unsigned short pcicmd = 0, tried_config = 0;	byte tmp = 0;	ide_hwif_t *hwif, *mate = NULL;	unsigned int class_rev;	static int secondpdc = 0;#ifdef CONFIG_IDEDMA_AUTO	if (!noautodma)		autodma = 1;#endif	if (pci_enable_device(dev)) {		printk("%s: error while enabling PCI device\n", d->name);		return;	}check_if_enabled:	if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {		printk("%s: error accessing PCI regs\n", d->name);		return;	}	if (!(pcicmd & PCI_COMMAND_IO)) {	/* is device disabled? */		/*		 * PnP BIOS was *supposed* to have set this device up for us,		 * but we can do it ourselves, so long as the BIOS has assigned an IRQ		 *  (or possibly the device is using a "legacy header" for IRQs).		 * Maybe the user deliberately *disabled* the device,		 * but we'll eventually ignore it again if no drives respond.		 */		if (tried_config++		 || ide_setup_pci_baseregs(dev, d->name)		 || pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {			printk("%s: device disabled (BIOS)\n", d->name);			return;		}		autodma = 0;	/* default DMA off if we had to configure it here */		goto check_if_enabled;	}	if (tried_config)