/* * linux/drivers/ide/ide-pmac.c * * Support for IDE interfaces on PowerMacs. * These IDE interfaces are memory-mapped and have a DBDMA channel * for doing DMA. * *  Copyright (C) 1998-2001 Paul Mackerras & Ben. Herrenschmidt * *  This program is free software; you can redistribute it and/or *  modify it under the terms of the GNU General Public License *  as published by the Free Software Foundation; either version *  2 of the License, or (at your option) any later version. * * Some code taken from drivers/ide/ide-dma.c: * *  Copyright (c) 1995-1998  Mark Lord * */#include <linux/config.h>#include <linux/types.h>#include <linux/kernel.h>#include <linux/sched.h>#include <linux/init.h>#include <linux/delay.h>#include <linux/ide.h>#include <linux/notifier.h>#include <linux/reboot.h>#include <asm/prom.h>#include <asm/io.h>#include <asm/dbdma.h>#include <asm/ide.h>#include <asm/mediabay.h>#include <asm/machdep.h>#include <asm/pmac_feature.h>#include <asm/sections.h>#include <asm/irq.h>#ifdef CONFIG_PMAC_PBOOK#include <linux/adb.h>#include <linux/pmu.h>#endif#include "ide_modes.h"extern char *ide_dmafunc_verbose(ide_dma_action_t dmafunc);extern void ide_do_request(ide_hwgroup_t *hwgroup, int masked_irq);#define IDE_PMAC_DEBUG#define DMA_WAIT_TIMEOUT	500struct pmac_ide_hwif {	ide_ioreg_t			regbase;	int				irq;	int				kind;	int				aapl_bus_id;	struct device_node*		node;	u32				timings[2];	struct resource*		reg_resource;#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC	volatile struct dbdma_regs*	dma_regs;	struct dbdma_cmd*		dma_table;	struct resource*		dma_resource;#endif	} pmac_ide[MAX_HWIFS] __pmacdata;static int pmac_ide_count;enum {	controller_ohare,	/* OHare based */	controller_heathrow,	/* Heathrow/Paddington */	controller_kl_ata3,	/* KeyLargo ATA-3 */	controller_kl_ata4,	/* KeyLargo ATA-4 */	controller_kl_ata4_80	/* KeyLargo ATA-4 with 80 conductor cable */};/* * Extra registers, both 32-bit little-endian */#define IDE_TIMING_CONFIG	0x200#define IDE_INTERRUPT		0x300/* * Timing configuration register definitions *//* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */#define SYSCLK_TICKS(t)		(((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)#define SYSCLK_TICKS_66(t)	(((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)#define IDE_SYSCLK_NS		30	/* 33Mhz cell */#define IDE_SYSCLK_66_NS	15	/* 66Mhz cell *//* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on * 40 connector cable and to 4 on 80 connector one. * Clock unit is 15ns (66Mhz) *  * 3 Values can be programmed: *  - Write data setup, which appears to match the cycle time. They *    also call it DIOW setup. *  - Ready to pause time (from spec) *  - Address setup. That one is weird. I don't see where exactly *    it fits in UDMA cycles, I got it's name from an obscure piece *    of commented out code in Darwin. They leave it to 0, we do as *    well, despite a comment that would lead to think it has a *    min value of 45ns. * Apple also add 60ns to the write data setup (or cycle time ?) on * reads. I can't explain that, I tried it and it broke everything * here. */#define TR_66_UDMA_MASK			0xfff00000#define TR_66_UDMA_EN			0x00100000 /* Enable Ultra mode for DMA */#define TR_66_UDMA_ADDRSETUP_MASK	0xe0000000 /* Address setup */#define TR_66_UDMA_ADDRSETUP_SHIFT	29#define TR_66_UDMA_RDY2PAUS_MASK	0x1e000000 /* Ready 2 pause time */#define TR_66_UDMA_RDY2PAUS_SHIFT	25#define TR_66_UDMA_WRDATASETUP_MASK	0x01e00000 /* Write data setup time */#define TR_66_UDMA_WRDATASETUP_SHIFT	21#define TR_66_MDMA_MASK			0x000ffc00#define TR_66_MDMA_RECOVERY_MASK	0x000f8000#define TR_66_MDMA_RECOVERY_SHIFT	15#define TR_66_MDMA_ACCESS_MASK		0x00007c00#define TR_66_MDMA_ACCESS_SHIFT		10#define TR_66_PIO_MASK			0x000003ff#define TR_66_PIO_RECOVERY_MASK		0x000003e0#define TR_66_PIO_RECOVERY_SHIFT	5#define TR_66_PIO_ACCESS_MASK		0x0000001f#define TR_66_PIO_ACCESS_SHIFT		0/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo * Can do pio & mdma modes, clock unit is 30ns (33Mhz) *  * The access time and recovery time can be programmed. Some older * Darwin code base limit OHare to 150ns cycle time. I decided to do * the same here fore safety against broken old hardware ;) * The HalfTick bit, when set, adds half a clock (15ns) to the access * time and removes one from recovery. It's not supported on KeyLargo * implementation afaik. The E bit appears to be set for PIO mode 0 and * is used to reach long timings used in this mode. */#define TR_33_MDMA_MASK			0x003ff800#define TR_33_MDMA_RECOVERY_MASK	0x001f0000#define TR_33_MDMA_RECOVERY_SHIFT	16#define TR_33_MDMA_ACCESS_MASK		0x0000f800#define TR_33_MDMA_ACCESS_SHIFT		11#define TR_33_MDMA_HALFTICK		0x00200000#define TR_33_PIO_MASK			0x000007ff#define TR_33_PIO_E			0x00000400#define TR_33_PIO_RECOVERY_MASK		0x000003e0#define TR_33_PIO_RECOVERY_SHIFT	5#define TR_33_PIO_ACCESS_MASK		0x0000001f#define TR_33_PIO_ACCESS_SHIFT		0/* * Interrupt register definitions */#define IDE_INTR_DMA			0x80000000#define IDE_INTR_DEVICE			0x40000000#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC/* Rounded Multiword DMA timings *  * I gave up finding a generic formula for all controller * types and instead, built tables based on timing values * used by Apple in Darwin's implementation. */struct mdma_timings_t {	int	accessTime;	int	recoveryTime;	int	cycleTime;};struct mdma_timings_t mdma_timings_33[] __pmacdata ={    { 240, 240, 480 },    { 180, 180, 360 },    { 135, 135, 270 },    { 120, 120, 240 },    { 105, 105, 210 },    {  90,  90, 180 },    {  75,  75, 150 },    {  75,  45, 120 },    {   0,   0,   0 }};struct mdma_timings_t mdma_timings_33k[] __pmacdata ={    { 240, 240, 480 },    { 180, 180, 360 },    { 150, 150, 300 },    { 120, 120, 240 },    {  90, 120, 210 },    {  90,  90, 180 },    {  90,  60, 150 },    {  90,  30, 120 },    {   0,   0,   0 }};struct mdma_timings_t mdma_timings_66[] __pmacdata ={    { 240, 240, 480 },    { 180, 180, 360 },    { 135, 135, 270 },    { 120, 120, 240 },    { 105, 105, 210 },    {  90,  90, 180 },    {  90,  75, 165 },    {  75,  45, 120 },    {   0,   0,   0 }};/* Ultra DMA timings (rounded) */struct {	int	addrSetup; /* ??? */	int	rdy2pause;	int	wrDataSetup;} udma_timings[] __pmacdata ={    {   0, 180,  120 },	/* Mode 0 */    {   0, 150,  90 },	/*      1 */    {   0, 120,  60 },	/*      2 */    {   0, 90,   45 },	/*      3 */    {   0, 90,   30 }	/*      4 */};/* allow up to 256 DBDMA commands per xfer */#define MAX_DCMDS		256/* Wait 2s for disk to answer on IDE bus after * enable operation. * NOTE: There is at least one case I know of a disk that needs about 10sec *       before anwering on the bus. I beleive we could add a kernel command *       line arg to override this delay for such cases. */#define IDE_WAKEUP_DELAY_MS	2000static void pmac_ide_setup_dma(struct device_node *np, int ix);static int pmac_ide_dmaproc(ide_dma_action_t func, ide_drive_t *drive);static int pmac_ide_build_dmatable(ide_drive_t *drive, int ix, int wr);static int pmac_ide_tune_chipset(ide_drive_t *drive, byte speed);static void pmac_ide_tuneproc(ide_drive_t *drive, byte pio);static void pmac_ide_selectproc(ide_drive_t *drive);#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */#ifdef CONFIG_PMAC_PBOOKstatic int idepmac_notify_sleep(struct pmu_sleep_notifier *self, int when);struct pmu_sleep_notifier idepmac_sleep_notifier = {	idepmac_notify_sleep, SLEEP_LEVEL_BLOCK,};#endif /* CONFIG_PMAC_PBOOK */static int pmac_ide_notify_reboot(struct notifier_block *, unsigned long, void *);static struct notifier_block pmac_ide_reboot_notifier = {	pmac_ide_notify_reboot,	NULL,	0};static int __pmacpmac_ide_find(ide_drive_t *drive){	ide_hwif_t *hwif = HWIF(drive);	ide_ioreg_t base;	int i;		for (i=0; i<pmac_ide_count; i++) {		base = pmac_ide[i].regbase;		if (base && base == hwif->io_ports[0])			return i;	}	return -1;}/* * N.B. this can't be an initfunc, because the media-bay task can * call ide_[un]register at any time. */void __pmacpmac_ide_init_hwif_ports(hw_regs_t *hw,			      ide_ioreg_t data_port, ide_ioreg_t ctrl_port,			      int *irq){	int i, ix;	if (data_port == 0)		return;	for (ix = 0; ix < MAX_HWIFS; ++ix)		if (data_port == pmac_ide[ix].regbase)			break;	if (ix >= MAX_HWIFS) {		/* Probably a PCI interface... */		for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)			hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;		hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;		return;	}	for (i = 0; i < 8; ++i)		hw->io_ports[i] = data_port + i * 0x10;	hw->io_ports[8] = data_port + 0x160;	if (irq != NULL)		*irq = pmac_ide[ix].irq;	ide_hwifs[ix].tuneproc = pmac_ide_tuneproc;	ide_hwifs[ix].selectproc = pmac_ide_selectproc;	ide_hwifs[ix].speedproc = &pmac_ide_tune_chipset;	if (pmac_ide[ix].dma_regs && pmac_ide[ix].dma_table) {		ide_hwifs[ix].dmaproc = &pmac_ide_dmaproc;#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC_AUTO		if (!noautodma)			ide_hwifs[ix].autodma = 1;#endif	}}#if 0/* This one could be later extended to handle CMD IDE and be used by some kind * of /proc interface. I want to be able to get the devicetree path of a block * device for yaboot configuration */struct device_node*pmac_ide_get_devnode(ide_drive_t *drive){	int i = pmac_ide_find(drive);	if (i < 0)		return NULL;	return pmac_ide[i].node;}#endif/* Setup timings for the selected drive (master/slave). I still need to verify if this * is enough, I beleive selectproc will be called whenever an IDE command is started, * but... */static void __pmacpmac_ide_selectproc(ide_drive_t *drive){	int i = pmac_ide_find(drive);	if (i < 0)		return;	if (drive->select.b.unit & 0x01)		out_le32((unsigned *)(IDE_DATA_REG + IDE_TIMING_CONFIG + _IO_BASE),			pmac_ide[i].timings[1]);	else		out_le32((unsigned *)(IDE_DATA_REG + IDE_TIMING_CONFIG + _IO_BASE),			pmac_ide[i].timings[0]);	(void)in_le32((unsigned *)(IDE_DATA_REG + IDE_TIMING_CONFIG + _IO_BASE));}/* Note: We don't use the generic routine here because for some * yet unexplained reasons, it cause some media-bay CD-ROMs to * lockup the bus. Strangely, this new version of the code is * almost identical to the generic one and works, I've not yet * managed to figure out what bit is causing the lockup in the * generic code, possibly a timing issue... *  * --BenH */static int __pmacwait_for_ready(ide_drive_t *drive){	/* Timeout bumped for some powerbooks */	int timeout = 2000;	byte stat;	while(--timeout) {		stat = GET_STAT();		if(!(stat & BUSY_STAT)) {			if (drive->ready_stat == 0)				break;			else if((stat & drive->ready_stat) || (stat & ERR_STAT))				break;		}		mdelay(1);	}	if((stat & ERR_STAT) || timeout <= 0) {		if (stat & ERR_STAT) {			printk(KERN_ERR "ide_pmac: wait_for_ready, error status: %x\n", stat);		}		return 1;	}	return 0;}static int __pmacpmac_ide_do_setfeature(ide_drive_t *drive, byte command){	int result = 1;	unsigned long flags;	ide_hwif_t *hwif = HWIF(drive);		disable_irq(hwif->irq);	/* disable_irq_nosync ?? */	udelay(1);	SELECT_DRIVE(HWIF(drive), drive);	SELECT_MASK(HWIF(drive), drive, 0);	udelay(1);	(void)GET_STAT(); /* Get rid of pending error state */	if(wait_for_ready(drive)) {		printk(KERN_ERR "pmac_ide_do_setfeature disk not ready before SET_FEATURE!\n");		goto out;	}	udelay(10);	OUT_BYTE(drive->ctl | 2, IDE_CONTROL_REG);	OUT_BYTE(command, IDE_NSECTOR_REG);	OUT_BYTE(SETFEATURES_XFER, IDE_FEATURE_REG);	OUT_BYTE(WIN_SETFEATURES, IDE_COMMAND_REG);	udelay(1);	__save_flags(flags);	/* local CPU only */	ide__sti();		/* local CPU only -- for jiffies */	result = wait_for_ready(drive);	__restore_flags(flags); /* local CPU only */	OUT_BYTE(drive->ctl, IDE_CONTROL_REG);	if (result)		printk(KERN_ERR "pmac_ide_do_setfeature disk not ready after SET_FEATURE !\n");out:	SELECT_MASK(HWIF(drive), drive, 0);	if (result == 0) {		drive->id->dma_ultra &= ~0xFF00;		drive->id->dma_mword &= ~0x0F00;		drive->id->dma_1word &= ~0x0F00;		switch(command) {			case XFER_UDMA_7:   drive->id->dma_ultra |= 0x8080; break;			case XFER_UDMA_6:   drive->id->dma_ultra |= 0x4040; break;			case XFER_UDMA_5:   drive->id->dma_ultra |= 0x2020; break;			case XFER_UDMA_4:   drive->id->dma_ultra |= 0x1010; break;			case XFER_UDMA_3:   drive->id->dma_ultra |= 0x0808; break;			case XFER_UDMA_2:   drive->id->dma_ultra |= 0x0404; break;			case XFER_UDMA_1:   drive->id->dma_ultra |= 0x0202; break;			case XFER_UDMA_0:   drive->id->dma_ultra |= 0x0101; break;			case XFER_MW_DMA_2: drive->id->dma_mword |= 0x0404; break;			case XFER_MW_DMA_1: drive->id->dma_mword |= 0x0202; break;			case XFER_MW_DMA_0: drive->id->dma_mword |= 0x0101; break;			case XFER_SW_DMA_2: drive->id->dma_1word |= 0x0404; break;			case XFER_SW_DMA_1: drive->id->dma_1word |= 0x0202; break;			case XFER_SW_DMA_0: drive->id->dma_1word |= 0x0101; break;			default: break;		}	}	enable_irq(hwif->irq);	return result;}/* Calculate PIO timings */static void __pmacpmac_ide_tuneproc(ide_drive_t *drive, byte pio){	ide_pio_data_t d;	int i;	u32 *timings;	unsigned accessTicks, recTicks;	unsigned accessTime, recTime;		i = pmac_ide_find(drive);	if (i < 0)		return;			pio = ide_get_best_pio_mode(drive, pio, 4, &d);	accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);	if (drive->select.b.unit & 0x01)		timings = &pmac_ide[i].timings[1];	else		timings = &pmac_ide[i].timings[0];	recTime = d.cycle_time - ide_pio_timings[pio].active_time			- ide_pio_timings[pio].setup_time;	recTime = max(recTime, 150U);	accessTime = ide_pio_timings[pio].active_time;	accessTime = max(accessTime, 150U);	if (pmac_ide[i].kind == controller_kl_ata4 ||		pmac_ide[i].kind == controller_kl_ata4_80) {		/* 66Mhz cell */		accessTicks = SYSCLK_TICKS_66(accessTime);		accessTicks = min(accessTicks, 0x1fU);		recTicks = SYSCLK_TICKS_66(recTime);		recTicks = min(recTicks, 0x1fU);		*timings = ((*timings) & ~TR_66_PIO_MASK) |				(accessTicks << TR_66_PIO_ACCESS_SHIFT) |				(recTicks << TR_66_PIO_RECOVERY_SHIFT);	} else {		/* 33Mhz cell */		int ebit = 0;		accessTicks = SYSCLK_TICKS(accessTime);		accessTicks = min(accessTicks, 0x1fU);		accessTicks = max(accessTicks, 4U);		recTicks = SYSCLK_TICKS(recTime);		recTicks = min(recTicks, 0x1fU);		recTicks = max(recTicks, 5U) - 4;		if (recTicks > 9) {			recTicks--; /* guess, but it's only for PIO0, so... */			ebit = 1;		}		*timings = ((*timings) & ~TR_33_PIO_MASK) |				(accessTicks << TR_33_PIO_ACCESS_SHIFT) |				(recTicks << TR_33_PIO_RECOVERY_SHIFT);		if (ebit)			*timings |= TR_33_PIO_E;	}#ifdef IDE_PMAC_DEBUG	printk(KERN_ERR "ide_pmac: Set PIO timing for mode %d, reg: 0x%08x\n",		pio,  *timings);#endif				if (drive->select.all == IN_BYTE(IDE_SELECT_REG))		pmac_ide_selectproc(drive);}#ifdef CONFIG_BLK_DEV_IDEDMA_PMACstatic int __pmacset_timings_udma(u32 *timings, byte speed){	unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;	rdyToPauseTicks = SYSCLK_TICKS_66(udma_timings[speed & 0xf].rdy2pause);	wrDataSetupTicks = SYSCLK_TICKS_66(udma_timings[speed & 0xf].wrDataSetup);	addrTicks = SYSCLK_TICKS_66(udma_timings[speed & 0xf].addrSetup);	*timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |			(wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) | 			(rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |			(addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |			TR_66_UDMA_EN;#ifdef IDE_PMAC_DEBUG	printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",		speed & 0xf,  *timings);#endif		return 0;}static int __pmacset_timings_mdma(int intf_type, u32 *timings, byte speed, int drive_cycle_time){	int cycleTime, accessTime, recTime;	unsigned accessTicks, recTicks;	struct mdma_timings_t* tm;	int i;	/* Get default cycle time for mode */	switch(speed & 0xf) {		case 0: cycleTime = 480; break;		case 1: cycleTime = 150; break;		case 2: cycleTime = 120; break;		default: