/* * MACRO DEFINITIONS FOR MODEM STATUS BITS */#define MODEMSTATUS_DTR 0x80#define MODEMSTATUS_DSR 0x40#define MODEMSTATUS_RTS 0x20#define MODEMSTATUS_CTS 0x10#define MODEMSTATUS_RI  0x04#define MODEMSTATUS_DCD 0x01/* * Channel Command/Address Register (CCAR) Command Codes */#define RTCmd_Null			0x0000#define RTCmd_ResetHighestIus		0x1000#define RTCmd_TriggerChannelLoadDma	0x2000#define RTCmd_TriggerRxDma		0x2800#define RTCmd_TriggerTxDma		0x3000#define RTCmd_TriggerRxAndTxDma		0x3800#define RTCmd_PurgeRxFifo		0x4800#define RTCmd_PurgeTxFifo		0x5000#define RTCmd_PurgeRxAndTxFifo		0x5800#define RTCmd_LoadRcc			0x6800#define RTCmd_LoadTcc			0x7000#define RTCmd_LoadRccAndTcc		0x7800#define RTCmd_LoadTC0			0x8800#define RTCmd_LoadTC1			0x9000#define RTCmd_LoadTC0AndTC1		0x9800#define RTCmd_SerialDataLSBFirst	0xa000#define RTCmd_SerialDataMSBFirst	0xa800#define RTCmd_SelectBigEndian		0xb000#define RTCmd_SelectLittleEndian	0xb800/* * DMA Command/Address Register (DCAR) Command Codes */#define DmaCmd_Null			0x0000#define DmaCmd_ResetTxChannel		0x1000#define DmaCmd_ResetRxChannel		0x1200#define DmaCmd_StartTxChannel		0x2000#define DmaCmd_StartRxChannel		0x2200#define DmaCmd_ContinueTxChannel	0x3000#define DmaCmd_ContinueRxChannel	0x3200#define DmaCmd_PauseTxChannel		0x4000#define DmaCmd_PauseRxChannel		0x4200#define DmaCmd_AbortTxChannel		0x5000#define DmaCmd_AbortRxChannel		0x5200#define DmaCmd_InitTxChannel		0x7000#define DmaCmd_InitRxChannel		0x7200#define DmaCmd_ResetHighestDmaIus	0x8000#define DmaCmd_ResetAllChannels		0x9000#define DmaCmd_StartAllChannels		0xa000#define DmaCmd_ContinueAllChannels	0xb000#define DmaCmd_PauseAllChannels		0xc000#define DmaCmd_AbortAllChannels		0xd000#define DmaCmd_InitAllChannels		0xf000#define TCmd_Null			0x0000#define TCmd_ClearTxCRC			0x2000#define TCmd_SelectTicrTtsaData		0x4000#define TCmd_SelectTicrTxFifostatus	0x5000#define TCmd_SelectTicrIntLevel		0x6000#define TCmd_SelectTicrdma_level		0x7000#define TCmd_SendFrame			0x8000#define TCmd_SendAbort			0x9000#define TCmd_EnableDleInsertion		0xc000#define TCmd_DisableDleInsertion	0xd000#define TCmd_ClearEofEom		0xe000#define TCmd_SetEofEom			0xf000#define RCmd_Null			0x0000#define RCmd_ClearRxCRC			0x2000#define RCmd_EnterHuntmode		0x3000#define RCmd_SelectRicrRtsaData		0x4000#define RCmd_SelectRicrRxFifostatus	0x5000#define RCmd_SelectRicrIntLevel		0x6000#define RCmd_SelectRicrdma_level		0x7000/* * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR) */ #define RECEIVE_STATUS		BIT5#define RECEIVE_DATA		BIT4#define TRANSMIT_STATUS		BIT3#define TRANSMIT_DATA		BIT2#define IO_PIN			BIT1#define MISC			BIT0/* * Receive status Bits in Receive Command/status Register RCSR */#define RXSTATUS_SHORT_FRAME		BIT8#define RXSTATUS_CODE_VIOLATION		BIT8#define RXSTATUS_EXITED_HUNT		BIT7#define RXSTATUS_IDLE_RECEIVED		BIT6#define RXSTATUS_BREAK_RECEIVED		BIT5#define RXSTATUS_ABORT_RECEIVED		BIT5#define RXSTATUS_RXBOUND		BIT4#define RXSTATUS_CRC_ERROR		BIT3#define RXSTATUS_FRAMING_ERROR		BIT3#define RXSTATUS_ABORT			BIT2#define RXSTATUS_PARITY_ERROR		BIT2#define RXSTATUS_OVERRUN		BIT1#define RXSTATUS_DATA_AVAILABLE		BIT0#define RXSTATUS_ALL			0x01f6#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )/* * Values for setting transmit idle mode in  * Transmit Control/status Register (TCSR) */#define IDLEMODE_FLAGS			0x0000#define IDLEMODE_ALT_ONE_ZERO		0x0100#define IDLEMODE_ZERO			0x0200#define IDLEMODE_ONE			0x0300#define IDLEMODE_ALT_MARK_SPACE		0x0500#define IDLEMODE_SPACE			0x0600#define IDLEMODE_MARK			0x0700#define IDLEMODE_MASK			0x0700/* * IUSC revision identifiers */#define	IUSC_SL1660			0x4d44#define IUSC_PRE_SL1660			0x4553/* * Transmit status Bits in Transmit Command/status Register (TCSR) */#define TCSR_PRESERVE			0x0F00#define TCSR_UNDERWAIT			BIT11#define TXSTATUS_PREAMBLE_SENT		BIT7#define TXSTATUS_IDLE_SENT		BIT6#define TXSTATUS_ABORT_SENT		BIT5#define TXSTATUS_EOF_SENT		BIT4#define TXSTATUS_EOM_SENT		BIT4#define TXSTATUS_CRC_SENT		BIT3#define TXSTATUS_ALL_SENT		BIT2#define TXSTATUS_UNDERRUN		BIT1#define TXSTATUS_FIFO_EMPTY		BIT0#define TXSTATUS_ALL			0x00fa#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )				#define MISCSTATUS_RXC_LATCHED		BIT15#define MISCSTATUS_RXC			BIT14#define MISCSTATUS_TXC_LATCHED		BIT13#define MISCSTATUS_TXC			BIT12#define MISCSTATUS_RI_LATCHED		BIT11#define MISCSTATUS_RI			BIT10#define MISCSTATUS_DSR_LATCHED		BIT9#define MISCSTATUS_DSR			BIT8#define MISCSTATUS_DCD_LATCHED		BIT7#define MISCSTATUS_DCD			BIT6#define MISCSTATUS_CTS_LATCHED		BIT5#define MISCSTATUS_CTS			BIT4#define MISCSTATUS_RCC_UNDERRUN		BIT3#define MISCSTATUS_DPLL_NO_SYNC		BIT2#define MISCSTATUS_BRG1_ZERO		BIT1#define MISCSTATUS_BRG0_ZERO		BIT0#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))#define SICR_RXC_ACTIVE			BIT15#define SICR_RXC_INACTIVE		BIT14#define SICR_RXC			(BIT15+BIT14)#define SICR_TXC_ACTIVE			BIT13#define SICR_TXC_INACTIVE		BIT12#define SICR_TXC			(BIT13+BIT12)#define SICR_RI_ACTIVE			BIT11#define SICR_RI_INACTIVE		BIT10#define SICR_RI				(BIT11+BIT10)#define SICR_DSR_ACTIVE			BIT9#define SICR_DSR_INACTIVE		BIT8#define SICR_DSR			(BIT9+BIT8)#define SICR_DCD_ACTIVE			BIT7#define SICR_DCD_INACTIVE		BIT6#define SICR_DCD			(BIT7+BIT6)#define SICR_CTS_ACTIVE			BIT5#define SICR_CTS_INACTIVE		BIT4#define SICR_CTS			(BIT5+BIT4)#define SICR_RCC_UNDERFLOW		BIT3#define SICR_DPLL_NO_SYNC		BIT2#define SICR_BRG1_ZERO			BIT1#define SICR_BRG0_ZERO			BIT0void usc_DisableMasterIrqBit( struct mgsl_struct *info );void usc_EnableMasterIrqBit( struct mgsl_struct *info );void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );#define usc_EnableInterrupts( a, b ) \	usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )#define usc_DisableInterrupts( a, b ) \	usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )#define usc_EnableMasterIrqBit(a) \	usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )#define usc_DisableMasterIrqBit(a) \	usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )/* * Transmit status Bits in Transmit Control status Register (TCSR) * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */#define TXSTATUS_PREAMBLE_SENT	BIT7#define TXSTATUS_IDLE_SENT	BIT6#define TXSTATUS_ABORT_SENT	BIT5#define TXSTATUS_EOF		BIT4#define TXSTATUS_CRC_SENT	BIT3#define TXSTATUS_ALL_SENT	BIT2#define TXSTATUS_UNDERRUN	BIT1#define TXSTATUS_FIFO_EMPTY	BIT0#define DICR_MASTER		BIT15#define DICR_TRANSMIT		BIT0#define DICR_RECEIVE		BIT1#define usc_EnableDmaInterrupts(a,b) \	usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )#define usc_DisableDmaInterrupts(a,b) \	usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )#define usc_EnableStatusIrqs(a,b) \	usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )#define usc_DisablestatusIrqs(a,b) \	usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )/* Transmit status Bits in Transmit Control status Register (TCSR) *//* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */#define DISABLE_UNCONDITIONAL    0#define DISABLE_END_OF_FRAME     1#define ENABLE_UNCONDITIONAL     2#define ENABLE_AUTO_CTS          3#define ENABLE_AUTO_DCD          3#define usc_EnableTransmitter(a,b) \	usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )#define usc_EnableReceiver(a,b) \	usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )u16  usc_InDmaReg( struct mgsl_struct *info, u16 Port );void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );u16  usc_InReg( struct mgsl_struct *info, u16 Port );void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );void usc_RCmd( struct mgsl_struct *info, u16 Cmd );void usc_TCmd( struct mgsl_struct *info, u16 Cmd );#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))void usc_process_rxoverrun_sync( struct mgsl_struct *info );void usc_start_receiver( struct mgsl_struct *info );void usc_stop_receiver( struct mgsl_struct *info );void usc_start_transmitter( struct mgsl_struct *info );void usc_stop_transmitter( struct mgsl_struct *info );void usc_set_txidle( struct mgsl_struct *info );void usc_load_txfifo( struct mgsl_struct *info );void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );void usc_enable_loopback( struct mgsl_struct *info, int enable );void usc_get_serial_signals( struct mgsl_struct *info );void usc_set_serial_signals( struct mgsl_struct *info );void usc_reset( struct mgsl_struct *info );void usc_set_sync_mode( struct mgsl_struct *info );void usc_set_sdlc_mode( struct mgsl_struct *info );void usc_set_async_mode( struct mgsl_struct *info );void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );void usc_loopback_frame( struct mgsl_struct *info );void mgsl_tx_timeout(unsigned long context);void usc_loopmode_cancel_transmit( struct mgsl_struct * info );void usc_loopmode_insert_request( struct mgsl_struct * info );int usc_loopmode_active( struct mgsl_struct * info);void usc_loopmode_send_done( struct mgsl_struct * info );int usc_loopmode_send_active( struct mgsl_struct * info );int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);#ifdef CONFIG_SYNCLINK_SYNCPPP/* SPPP/HDLC stuff */void mgsl_sppp_init(struct mgsl_struct *info);void mgsl_sppp_delete(struct mgsl_struct *info);int mgsl_sppp_open(struct net_device *d);int mgsl_sppp_close(struct net_device *d);void mgsl_sppp_tx_timeout(struct net_device *d);int mgsl_sppp_tx(struct sk_buff *skb, struct net_device *d);void mgsl_sppp_rx_done(struct mgsl_struct *info, char *buf, int size);void mgsl_sppp_tx_done(struct mgsl_struct *info);int mgsl_sppp_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);struct net_device_stats *mgsl_net_stats(struct net_device *dev);#endif/* * Defines a BUS descriptor value for the PCI adapter * local bus address ranges. */#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \(0x00400020 + \((WrHold) << 30) + \((WrDly)  << 28) + \((RdDly)  << 26) + \((Nwdd)   << 20) + \((Nwad)   << 15) + \((Nxda)   << 13) + \((Nrdd)   << 11) + \((Nrad)   <<  6) )void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);/* * Adapter diagnostic routines */BOOLEAN mgsl_register_test( struct mgsl_struct *info );BOOLEAN mgsl_irq_test( struct mgsl_struct *info );BOOLEAN mgsl_dma_test( struct mgsl_struct *info );BOOLEAN mgsl_memory_test( struct mgsl_struct *info );int mgsl_adapter_test( struct mgsl_struct *info );/* * device and resource management routines */int mgsl_claim_resources(struct mgsl_struct *info);void mgsl_release_resources(struct mgsl_struct *info);void mgsl_add_device(struct mgsl_struct *info);struct mgsl_struct* mgsl_allocate_device(void);int mgsl_enum_isa_devices(void);/* * DMA buffer manupulation functions. */void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );int  mgsl_get_rx_frame( struct mgsl_struct *info );int  mgsl_get_raw_rx_frame( struct mgsl_struct *info );void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );int num_free_tx_dma_buffers(struct mgsl_struct *info);void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);/* * DMA and Shared Memory buffer allocation and formatting */int  mgsl_allocate_dma_buffers(struct mgsl_struct *info);void mgsl_free_dma_buffers(struct mgsl_struct *info);int  mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);int  mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);void mgsl_free_buffer_list_memory(struct mgsl_struct *info);int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);int load_next_tx_holding_buffer(struct mgsl_struct *info);int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);/* * Bottom half interrupt handlers */void mgsl_bh_handler(void* Context);void mgsl_bh_receive(struct mgsl_struct *info);void mgsl_bh_transmit(struct mgsl_struct *info);void mgsl_bh_status(struct mgsl_struct *info);/* * Interrupt handler routines and dispatch table. */void mgsl_isr_null( struct mgsl_struct *info );void mgsl_isr_transmit_data( struct mgsl_struct *info );void mgsl_isr_receive_data( struct mgsl_struct *info );void mgsl_isr_receive_status( struct mgsl_struct *info );void mgsl_isr_transmit_status( struct mgsl_struct *info );void mgsl_isr_io_pin( struct mgsl_struct *info );void mgsl_isr_misc( struct mgsl_struct *info );void mgsl_isr_receive_dma( struct mgsl_struct *info );void mgsl_isr_transmit_dma( struct mgsl_struct *info );typedef void (*isr_dispatch_func)(struct mgsl_struct *);isr_dispatch_func UscIsrTable[7] ={	mgsl_isr_null,	mgsl_isr_misc,	mgsl_isr_io_pin,	mgsl_isr_transmit_data,	mgsl_isr_transmit_status,	mgsl_isr_receive_data,	mgsl_isr_receive_status};/* * ioctl call handlers */static int set_modem_info(struct mgsl_struct * info, unsigned int cmd,			  unsigned int *value);static int get_modem_info(struct mgsl_struct * info, unsigned int *value);static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount	*user_icount);static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS *user_params);static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS *new_params);static int mgsl_get_txidle(struct mgsl_struct * info, int*idle_mode);static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);