/*	drivers/net/tulip/media.c	Maintained by Jeff Garzik <jgarzik@mandrakesoft.com>	Copyright 2000,2001  The Linux Kernel Team	Written/copyright 1994-2001 by Donald Becker.	This software may be used and distributed according to the terms	of the GNU General Public License, incorporated herein by reference.	Please refer to Documentation/DocBook/tulip.{pdf,ps,html}	for more information on this driver, or visit the project	Web page at http://sourceforge.net/projects/tulip/*/#include <linux/kernel.h>#include <linux/mii.h>#include <linux/init.h>#include <linux/delay.h>#include "tulip.h"/* This is a mysterious value that can be written to CSR11 in the 21040 (only)   to support a pre-NWay full-duplex signaling mechanism using short frames.   No one knows what it should be, but if left at its default value some   10base2(!) packets trigger a full-duplex-request interrupt. */#define FULL_DUPLEX_MAGIC	0x6969/* The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually   met by back-to-back PCI I/O cycles, but we insert a delay to avoid   "overclocking" issues or future 66Mhz PCI. */#define mdio_delay() inl(mdio_addr)/* Read and write the MII registers using software-generated serial   MDIO protocol.  It is just different enough from the EEPROM protocol   to not share code.  The maxium data clock rate is 2.5 Mhz. */#define MDIO_SHIFT_CLK		0x10000#define MDIO_DATA_WRITE0	0x00000#define MDIO_DATA_WRITE1	0x20000#define MDIO_ENB		0x00000 /* Ignore the 0x02000 databook setting. */#define MDIO_ENB_IN		0x40000#define MDIO_DATA_READ		0x80000static const unsigned char comet_miireg2offset[32] = {	0xB4, 0xB8, 0xBC, 0xC0,  0xC4, 0xC8, 0xCC, 0,  0,0,0,0,  0,0,0,0,	0,0xD0,0,0,  0,0,0,0,  0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };/* MII transceiver control section.   Read and write the MII registers using software-generated serial   MDIO protocol.  See the MII specifications or DP83840A data sheet   for details. */int tulip_mdio_read(struct net_device *dev, int phy_id, int location){	struct tulip_private *tp = (struct tulip_private *)dev->priv;	int i;	int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location;	int retval = 0;	long ioaddr = dev->base_addr;	long mdio_addr = ioaddr + CSR9;	unsigned long flags;	if (location & ~0x1f)		return 0xffff;	if (tp->chip_id == COMET  &&  phy_id == 30) {		if (comet_miireg2offset[location])			return inl(ioaddr + comet_miireg2offset[location]);		return 0xffff;	}	spin_lock_irqsave(&tp->mii_lock, flags);	if (tp->chip_id == LC82C168) {		int i = 1000;		outl(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);		inl(ioaddr + 0xA0);		inl(ioaddr + 0xA0);		while (--i > 0) {			barrier();			if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000))				break;		}		spin_unlock_irqrestore(&tp->mii_lock, flags);		return retval & 0xffff;	}	/* Establish sync by sending at least 32 logic ones. */	for (i = 32; i >= 0; i--) {		outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);		mdio_delay();		outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);		mdio_delay();	}	/* Shift the read command bits out. */	for (i = 15; i >= 0; i--) {		int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;		outl(MDIO_ENB | dataval, mdio_addr);		mdio_delay();		outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);		mdio_delay();	}	/* Read the two transition, 16 data, and wire-idle bits. */	for (i = 19; i > 0; i--) {		outl(MDIO_ENB_IN, mdio_addr);		mdio_delay();		retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);		outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);		mdio_delay();	}	spin_unlock_irqrestore(&tp->mii_lock, flags);	return (retval>>1) & 0xffff;}void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val){	struct tulip_private *tp = (struct tulip_private *)dev->priv;	int i;	int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff);	long ioaddr = dev->base_addr;	long mdio_addr = ioaddr + CSR9;	unsigned long flags;	if (location & ~0x1f)		return;	if (tp->chip_id == COMET && phy_id == 30) {		if (comet_miireg2offset[location])			outl(val, ioaddr + comet_miireg2offset[location]);		return;	}	spin_lock_irqsave(&tp->mii_lock, flags);	if (tp->chip_id == LC82C168) {		int i = 1000;		outl(cmd, ioaddr + 0xA0);		do {			barrier();			if ( ! (inl(ioaddr + 0xA0) & 0x80000000))				break;		} while (--i > 0);		spin_unlock_irqrestore(&tp->mii_lock, flags);		return;	}	/* Establish sync by sending 32 logic ones. */	for (i = 32; i >= 0; i--) {		outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);		mdio_delay();		outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);		mdio_delay();	}	/* Shift the command bits out. */	for (i = 31; i >= 0; i--) {		int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;		outl(MDIO_ENB | dataval, mdio_addr);		mdio_delay();		outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);		mdio_delay();	}	/* Clear out extra bits. */	for (i = 2; i > 0; i--) {		outl(MDIO_ENB_IN, mdio_addr);		mdio_delay();		outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);		mdio_delay();	}	spin_unlock_irqrestore(&tp->mii_lock, flags);}/* Set up the transceiver control registers for the selected media type. */void tulip_select_media(struct net_device *dev, int startup){	long ioaddr = dev->base_addr;	struct tulip_private *tp = (struct tulip_private *)dev->priv;	struct mediatable *mtable = tp->mtable;	u32 new_csr6;	int i;	if (mtable) {		struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];		unsigned char *p = mleaf->leafdata;		switch (mleaf->type) {		case 0:					/* 21140 non-MII xcvr. */			if (tulip_debug > 1)				printk(KERN_DEBUG "%s: Using a 21140 non-MII transceiver"					   " with control setting %2.2x.\n",					   dev->name, p[1]);			dev->if_port = p[0];			if (startup)				outl(mtable->csr12dir | 0x100, ioaddr + CSR12);			outl(p[1], ioaddr + CSR12);			new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);			break;		case 2: case 4: {			u16 setup[5];			u32 csr13val, csr14val, csr15dir, csr15val;			for (i = 0; i < 5; i++)				setup[i] = get_u16(&p[i*2 + 1]);			dev->if_port = p[0] & MEDIA_MASK;			if (tulip_media_cap[dev->if_port] & MediaAlwaysFD)				tp->full_duplex = 1;			if (startup && mtable->has_reset) {				struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];				unsigned char *rst = rleaf->leafdata;				if (tulip_debug > 1)					printk(KERN_DEBUG "%s: Resetting the transceiver.\n",						   dev->name);				for (i = 0; i < rst[0]; i++)					outl(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);			}			if (tulip_debug > 1)				printk(KERN_DEBUG "%s: 21143 non-MII %s transceiver control "					   "%4.4x/%4.4x.\n",					   dev->name, medianame[dev->if_port], setup[0], setup[1]);			if (p[0] & 0x40) {	/* SIA (CSR13-15) setup values are provided. */				csr13val = setup[0];				csr14val = setup[1];				csr15dir = (setup[3]<<16) | setup[2];				csr15val = (setup[4]<<16) | setup[2];				outl(0, ioaddr + CSR13);				outl(csr14val, ioaddr + CSR14);				outl(csr15dir, ioaddr + CSR15);	/* Direction */				outl(csr15val, ioaddr + CSR15);	/* Data */				outl(csr13val, ioaddr + CSR13);			} else {				csr13val = 1;				csr14val = 0;				csr15dir = (setup[0]<<16) | 0x0008;				csr15val = (setup[1]<<16) | 0x0008;				if (dev->if_port <= 4)					csr14val = t21142_csr14[dev->if_port];				if (startup) {					outl(0, ioaddr + CSR13);					outl(csr14val, ioaddr + CSR14);				}				outl(csr15dir, ioaddr + CSR15);	/* Direction */				outl(csr15val, ioaddr + CSR15);	/* Data */				if (startup) outl(csr13val, ioaddr + CSR13);			}			if (tulip_debug > 1)				printk(KERN_DEBUG "%s:  Setting CSR15 to %8.8x/%8.8x.\n",					   dev->name, csr15dir, csr15val);			if (mleaf->type == 4)				new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);			else				new_csr6 = 0x82420000;			break;		}		case 1: case 3: {			int phy_num = p[0];			int init_length = p[1];			u16 *misc_info, tmp_info;			dev->if_port = 11;			new_csr6 = 0x020E0000;			if (mleaf->type == 3) {	/* 21142 */				u16 *init_sequence = (u16*)(p+2);				u16 *reset_sequence = &((u16*)(p+3))[init_length];				int reset_length = p[2 + init_length*2];				misc_info = reset_sequence + reset_length;				if (startup)					for (i = 0; i < reset_length; i++)						outl(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);				for (i = 0; i < init_length; i++)					outl(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);			} else {				u8 *init_sequence = p + 2;				u8 *reset_sequence = p + 3 + init_length;				int reset_length = p[2 + init_length];				misc_info = (u16*)(reset_sequence + reset_length);				if (startup) {					outl(mtable->csr12dir | 0x100, ioaddr + CSR12);					for (i = 0; i < reset_length; i++)						outl(reset_sequence[i], ioaddr + CSR12);