/* * $Id: dmascc.c,v 1.27 2000/06/01 14:46:23 oe1kib Exp $ * * Driver for high-speed SCC boards (those with DMA support) * Copyright (C) 1997-2000 Klaus Kudielka * * S5SCC/DMA support by Janko Koleznik S52HI * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * */#include <linux/module.h>#include <linux/delay.h>#include <linux/errno.h>#include <linux/if_arp.h>#include <linux/in.h>#include <linux/init.h>#include <linux/interrupt.h>#include <linux/ioport.h>#include <linux/kernel.h>#include <linux/mm.h>#include <linux/netdevice.h>#include <linux/rtnetlink.h>#include <linux/sockios.h>#include <linux/tqueue.h>#include <linux/version.h>#include <asm/atomic.h>#include <asm/bitops.h>#include <asm/dma.h>#include <asm/io.h>#include <asm/irq.h>#include <asm/segment.h>#include <asm/uaccess.h>#include <net/ax25.h>#include "z8530.h"/* Linux 2.2 and 2.3 compatibility */#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14)#define net_device device#endif#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43)#define netif_start_queue(dev) { dev->tbusy = 0; }#define netif_stop_queue(dev) { dev->tbusy = 1; }#define netif_wake_queue(dev) { dev->tbusy = 0; mark_bh(NET_BH); }#endif#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,47)#define netif_running(dev) (dev->flags & IFF_UP)#endif/* Number of buffers per channel */#define NUM_TX_BUF      2          /* NUM_TX_BUF >= 1 (min. 2 recommended) */#define NUM_RX_BUF      6          /* NUM_RX_BUF >= 1 (min. 2 recommended) */#define BUF_SIZE        1576       /* BUF_SIZE >= mtu + hard_header_len *//* Cards supported */#define HW_PI           { "Ottawa PI", 0x300, 0x20, 0x10, 8, \                            0, 8, 1843200, 3686400 }#define HW_PI2          { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \			    0, 8, 3686400, 7372800 }#define HW_TWIN         { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \			    0, 4, 6144000, 6144000 }#define HW_S5           { "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \                          0, 8, 4915200, 9830400 }#define HARDWARE        { HW_PI, HW_PI2, HW_TWIN, HW_S5 }#define TMR_0_HZ        25600      /* Frequency of timer 0 */#define TYPE_PI         0#define TYPE_PI2        1#define TYPE_TWIN       2#define TYPE_S5         3#define NUM_TYPES       4#define MAX_NUM_DEVS    32/* SCC chips supported */#define Z8530           0#define Z85C30          1#define Z85230          2#define CHIPNAMES       { "Z8530", "Z85C30", "Z85230" }/* I/O registers *//* 8530 registers relative to card base */#define SCCB_CMD        0x00#define SCCB_DATA       0x01#define SCCA_CMD        0x02#define SCCA_DATA       0x03/* 8253/8254 registers relative to card base */#define TMR_CNT0        0x00#define TMR_CNT1        0x01#define TMR_CNT2        0x02#define TMR_CTRL        0x03/* Additional PI/PI2 registers relative to card base */#define PI_DREQ_MASK    0x04/* Additional PackeTwin registers relative to card base */#define TWIN_INT_REG    0x08#define TWIN_CLR_TMR1   0x09#define TWIN_CLR_TMR2   0x0a#define TWIN_SPARE_1    0x0b#define TWIN_DMA_CFG    0x08#define TWIN_SERIAL_CFG 0x09#define TWIN_DMA_CLR_FF 0x0a#define TWIN_SPARE_2    0x0b/* PackeTwin I/O register values *//* INT_REG */#define TWIN_SCC_MSK       0x01#define TWIN_TMR1_MSK      0x02#define TWIN_TMR2_MSK      0x04#define TWIN_INT_MSK       0x07/* SERIAL_CFG */#define TWIN_DTRA_ON       0x01#define TWIN_DTRB_ON       0x02#define TWIN_EXTCLKA       0x04#define TWIN_EXTCLKB       0x08#define TWIN_LOOPA_ON      0x10#define TWIN_LOOPB_ON      0x20#define TWIN_EI            0x80/* DMA_CFG */#define TWIN_DMA_HDX_T1    0x08#define TWIN_DMA_HDX_R1    0x0a#define TWIN_DMA_HDX_T3    0x14#define TWIN_DMA_HDX_R3    0x16#define TWIN_DMA_FDX_T3R1  0x1b#define TWIN_DMA_FDX_T1R3  0x1d/* Status values */#define IDLE      0#define TX_HEAD   1#define TX_DATA   2#define TX_PAUSE  3#define TX_TAIL   4#define RTS_OFF   5#define WAIT      6#define DCD_ON    7#define RX_ON     8#define DCD_OFF   9/* Ioctls */#define SIOCGSCCPARAM SIOCDEVPRIVATE#define SIOCSSCCPARAM (SIOCDEVPRIVATE+1)/* Data types */struct scc_param {  int pclk_hz;    /* frequency of BRG input (don't change) */  int brg_tc;     /* BRG terminal count; BRG disabled if < 0 */  int nrzi;       /* 0 (nrz), 1 (nrzi) */  int clocks;     /* see dmascc_cfg documentation */  int txdelay;    /* [1/TMR_0_HZ] */  int txtimeout;  /* [1/HZ] */  int txtail;     /* [1/TMR_0_HZ] */  int waittime;   /* [1/TMR_0_HZ] */  int slottime;   /* [1/TMR_0_HZ] */  int persist;    /* 1 ... 256 */  int dma;        /* -1 (disable), 0, 1, 3 */  int txpause;    /* [1/TMR_0_HZ] */  int rtsoff;     /* [1/TMR_0_HZ] */  int dcdon;      /* [1/TMR_0_HZ] */  int dcdoff;     /* [1/TMR_0_HZ] */};struct scc_hardware {  char *name;  int io_region;  int io_delta;  int io_size;  int num_devs;  int scc_offset;  int tmr_offset;  int tmr_hz;  int pclk_hz;};struct scc_priv {#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)  char name[IFNAMSIZ];#endif  int type;  int chip;  struct net_device *dev;  struct scc_info *info;  struct net_device_stats stats;  int channel;  int card_base, scc_cmd, scc_data;  int tmr_cnt, tmr_ctrl, tmr_mode;  struct scc_param param;  char rx_buf[NUM_RX_BUF][BUF_SIZE];  int rx_len[NUM_RX_BUF];  int rx_ptr;  struct tq_struct rx_task;  int rx_head, rx_tail, rx_count;  int rx_over;  char tx_buf[NUM_TX_BUF][BUF_SIZE];  int tx_len[NUM_TX_BUF];  int tx_ptr;  int tx_head, tx_tail, tx_count;  int state;  unsigned long tx_start;  int rr0;};struct scc_info {  int irq_used;  int twin_serial_cfg;  struct net_device dev[2];  struct scc_priv priv[2];  struct scc_info *next;};/* Function declarations */int dmascc_init(void) __init;static int setup_adapter(int card_base, int type, int n) __init;static void write_scc(struct scc_priv *priv, int reg, int val);static void write_scc_data(struct scc_priv *priv, int val, int fast);static int read_scc(struct scc_priv *priv, int reg);static int read_scc_data(struct scc_priv *priv);static int scc_open(struct net_device *dev);static int scc_close(struct net_device *dev);static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);static int scc_send_packet(struct sk_buff *skb, struct net_device *dev);static struct net_device_stats *scc_get_stats(struct net_device *dev);static int scc_set_mac_address(struct net_device *dev, void *sa);static void scc_isr(int irq, void *dev_id, struct pt_regs * regs);static inline void z8530_isr(struct scc_info *info);static void rx_isr(struct scc_priv *priv);static void special_condition(struct scc_priv *priv, int rc);static void rx_bh(void *arg);static void tx_isr(struct scc_priv *priv);static void es_isr(struct scc_priv *priv);static void tm_isr(struct scc_priv *priv);static inline void tx_on(struct scc_priv *priv);static inline void rx_on(struct scc_priv *priv);static inline void rx_off(struct scc_priv *priv);static void start_timer(struct scc_priv *priv, int t, int r15);static inline unsigned char random(void);/* Initialization variables */static int io[MAX_NUM_DEVS] __initdata = { 0, };/* Beware! hw[] is also used in cleanup_module(). If __initdata also applies   to modules, we may not declare hw[] as __initdata */static struct scc_hardware hw[NUM_TYPES] __initdata = HARDWARE;static char ax25_broadcast[7] __initdata =  { 'Q'<<1, 'S'<<1, 'T'<<1, ' '<<1, ' '<<1, ' '<<1, '0'<<1 };static char ax25_test[7] __initdata =  { 'L'<<1, 'I'<<1, 'N'<<1, 'U'<<1, 'X'<<1, ' '<<1, '1'<<1 };/* Global variables */static struct scc_info *first;static unsigned long rand;/* Module functions */#ifdef MODULEMODULE_AUTHOR("Klaus Kudielka");MODULE_DESCRIPTION("Driver for high-speed SCC boards");MODULE_PARM(io, "1-" __MODULE_STRING(MAX_NUM_DEVS) "i");MODULE_LICENSE("GPL");int init_module(void) {  return dmascc_init();}void cleanup_module(void) {  int i;  struct scc_info *info;  while (first) {    info = first;    /* Unregister devices */    for (i = 0; i < 2; i++) {      if (info->dev[i].name)	rtnl_lock();	unregister_netdevice(&info->dev[i]);	rtnl_unlock();    }    /* Reset board */    if (info->priv[0].type == TYPE_TWIN)      outb(0, info->dev[0].base_addr + TWIN_SERIAL_CFG);    write_scc(&info->priv[0], R9, FHWRES);    release_region(info->dev[0].base_addr,		   hw[info->priv[0].type].io_size);    /* Free memory */    first = info->next;    kfree(info);  }}#elsevoid __init dmascc_setup(char *str, int *ints) {   int i;   for (i = 0; i < MAX_NUM_DEVS && i < ints[0]; i++)      io[i] = ints[i+1];}#endif/* Initialization functions */int __init dmascc_init(void) {  int h, i, j, n;  int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS],    t1[MAX_NUM_DEVS];  unsigned t_val;  unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS],    counting[MAX_NUM_DEVS];  /* Initialize random number generator */  rand = jiffies;  /* Cards found = 0 */  n = 0;  /* Warning message */  if (!io[0]) printk("dmascc: autoprobing (dangerous)\n");  /* Run autodetection for each card type */  for (h = 0; h < NUM_TYPES; h++) {    if (io[0]) {      /* User-specified I/O address regions */      for (i = 0; i < hw[h].num_devs; i++) base[i] = 0;      for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {	j = (io[i] - hw[h].io_region) / hw[h].io_delta;	if (j >= 0 &&	    j < hw[h].num_devs && 	    hw[h].io_region + j * hw[h].io_delta == io[i]) {	  base[j] = io[i];	}      }    } else {      /* Default I/O address regions */      for (i = 0; i < hw[h].num_devs; i++) {	base[i] = hw[h].io_region + i * hw[h].io_delta;      }    }    /* Check valid I/O address regions */    for (i = 0; i < hw[h].num_devs; i++)      if (base[i]) {	if (check_region(base[i], hw[h].io_size))	  base[i] = 0;	else {	  tcmd[i] = base[i] + hw[h].tmr_offset + TMR_CTRL;	  t0[i]   = base[i] + hw[h].tmr_offset + TMR_CNT0;	  t1[i]   = base[i] + hw[h].tmr_offset + TMR_CNT1;	}      }    /* Start timers */    for (i = 0; i < hw[h].num_devs; i++)      if (base[i]) {	/* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */	outb(0x36, tcmd[i]);	outb((hw[h].tmr_hz/TMR_0_HZ) & 0xFF, t0[i]);	outb((hw[h].tmr_hz/TMR_0_HZ) >> 8, t0[i]);	/* Timer 1: LSB+MSB, Mode 0, HZ/10 */	outb(0x70, tcmd[i]);	outb((TMR_0_HZ/HZ*10) & 0xFF, t1[i]);	outb((TMR_0_HZ/HZ*10) >> 8, t1[i]);	start[i] = jiffies;	delay[i] = 0;	counting[i] = 1;	/* Timer 2: LSB+MSB, Mode 0 */	outb(0xb0, tcmd[i]);      }    time = jiffies;    /* Wait until counter registers are loaded */    udelay(2000000/TMR_0_HZ);    /* Timing loop */    while (jiffies - time < 13) {      for (i = 0; i < hw[h].num_devs; i++)	if (base[i] && counting[i]) {	  /* Read back Timer 1: latch; read LSB; read MSB */	  outb(0x40, tcmd[i]);	  t_val = inb(t1[i]) + (inb(t1[i]) << 8);	  /* Also check whether counter did wrap */	  if (t_val == 0 || t_val > TMR_0_HZ/HZ*10) counting[i] = 0;	  delay[i] = jiffies - start[i];	}    }    /* Evaluate measurements */    for (i = 0; i < hw[h].num_devs; i++)      if (base[i]) {	if (delay[i] >= 9 && delay[i] <= 11) {	  /* Ok, we have found an adapter */	  if (setup_adapter(base[i], h, n) == 0)	    n++;	}      }  } /* NUM_TYPES */  /* If any adapter was successfully initialized, return ok */  if (n) return 0;  /* If no adapter found, return error */  printk("dmascc: no adapters found\n");  return -EIO;}int __init setup_adapter(int card_base, int type, int n) {  int i, irq, chip;  struct scc_info *info;  struct net_device *dev;  struct scc_priv *priv;  unsigned long time;  unsigned int irqs;  int tmr_base = card_base + hw[type].tmr_offset;