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--
-- Title       : Test Bench for counter
-- Design      : UART
-- Author      : Xinghua Lou
-- Company     : Tsinghua University
--
---------------------------------------------------------------------------------------------------
--
-- File        : $DSN\src\TestBench\counter_TB.vhd
-- Generated   : 4/12/2005, 4:11 PM
-- From        : $DSN\src\counter.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
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--
-- Description : Automatically generated Test Bench for counter_tb
--
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library ieee;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity counter_tb is
	-- Generic declarations of the tested unit
		generic(
		MAX_COUNT : INTEGER := 10 );
end counter_tb;

architecture TB_ARCHITECTURE of counter_tb is
	-- Component declaration of the tested unit
	component counter
		generic(
		MAX_COUNT : INTEGER := 10 );
	port(
		clk : in std_logic;
		reset_n : in std_logic;
		ce : in std_logic;
		overflow : out std_logic );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clk : std_logic := '0';
	signal reset_n : std_logic;
	signal ce : std_logic;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal overflow : std_logic;

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : counter
		generic map (
			MAX_COUNT => MAX_COUNT
		)

		port map (
			clk => clk,
			reset_n => reset_n,
			ce => ce,
			overflow => overflow
		);

	-- Add your stimulus here ...
	-- 產生時鐘信號
	clk_gen : process
	begin
		clk <= not clk;
		wait for 50 ns;
	end process;

	-- 測試主流程
	main: process
	begin
		reset_n <= '0';
		ce <= '0';	
		wait for 100 ns;
		reset_n <= '1';
		ce <= '1';
		
		wait;
		
	end process;
	
end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_counter of counter_tb is
	for TB_ARCHITECTURE
		for UUT : counter
			use entity work.counter(counter);
		end for;
	end for;
end TESTBENCH_FOR_counter;