LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY divclk IS
PORT(	clk		:	IN	STD_LOGIC;
		clk1	:	OUT STD_LOGIC;
		clk2	:	OUT	STD_LOGIC;
		clk3	:	OUT	STD_LOGIC;
		clk4	:	OUT STD_LOGIC
	);

	CONSTANT number1 : INTEGER :=5000;
	CONSTANT number2 : INTEGER :=50;
	CONSTANT number3 : INTEGER :=5;
	CONSTANT number4 : INTEGER :=4;
	
END divclk;

ARCHITECTURE func1 OF divclk IS
SIGNAL temp1:	STD_LOGIC;
SIGNAL temp2:	STD_LOGIC;
SIGNAL temp3:	STD_LOGIC;
SIGNAL temp4:	STD_LOGIC;
BEGIN
	clk4	<= temp1;	--1ms
	clk3	<= temp2;	--50ms
	clk2	<= temp3;	--0.25s
	clk1	<= temp4;	--1s

	PROCESS(clk)
	VARIABLE  counter1 : INTEGER RANGE 0 TO 8191;
	VARIABLE  counter2 : INTEGER RANGE 0 TO 63;
	VARIABLE  counter3 : INTEGER RANGE 0 TO 7;
	VARIABLE  counter4 : INTEGER RANGE 0 TO 7;
	BEGIN
		IF(clk'EVENT AND clk = '1') THEN
			counter1 := counter1 + 1;
			IF(counter1 = number1) THEN
				counter2 := counter2 + 1;
				IF(counter2 = number2) THEN
					counter3 := counter3 + 1;
					IF(counter3 = number3) THEN
						counter4 := counter4 + 1;
						IF(counter4 = number4) THEN
							temp4 <= NOT temp4;
							counter4 := 0;
						END IF;
						temp3 <= NOT temp3;
						counter3 := 0;
					END IF;
					temp2 <= NOT temp2;
					counter2 := 0;
				END IF;
			temp1 <= NOT temp1;
			counter1 := 0;
			END IF;
		END IF;
	END PROCESS;
END func1;