# frv testcase for ftigt $FCCi_2,$GRi,$s12# mach: all	.include "testutils.inc"	start	.global ftigtftigt:	and_spr_immed	-4081,tbr		; clear tbr.tt	set_gr_spr	tbr,gr7	inc_gr_immed	2112,gr7		; address of exception handler	set_bctrlr_0_0	gr7	; bctrlr 0,0	set_spr_immed	128,lcr	set_gr_immed	0,gr7	set_spr_addr	bad,lr	set_fcc		0x0 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_fcc		0x1 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	set_psr_et	1	set_spr_addr	ok2,lr	set_fcc		0x2 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	failok2:	set_psr_et	1	set_spr_addr	ok3,lr	set_fcc		0x3 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	failok3:	set_spr_addr	bad,lr	set_fcc		0x4 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_fcc		0x5 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	set_psr_et	1	set_spr_addr	ok6,lr	set_fcc		0x6 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	failok6:	set_psr_et	1	set_spr_addr	ok7,lr	set_fcc		0x7 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	failok7:	set_spr_addr	bad,lr	set_fcc		0x8 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_fcc		0x9 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	set_psr_et	1	set_spr_addr	oka,lr	set_fcc		0xa 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	failoka:	set_psr_et	1	set_spr_addr	okb,lr	set_fcc		0xb 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	failokb:	set_spr_addr	bad,lr	set_fcc		0xc 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_fcc		0xd 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	set_psr_et	1	set_spr_addr	oke,lr	set_fcc		0xe 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	failoke:	set_psr_et	1	set_spr_addr	okf,lr	set_fcc		0xf 0	ftigt 		fcc0,gr7,4	; should branch to tbr + (128 + 4)*16	failokf:	passbad:	fail